IP Library Granted Patent US 8,988,641
Granted Patent B2
US 8,988,641 · App. 14/286,288 · Granted Mar 24, 2015

Liquid crystal display device and method for manufacturing liquid crystal display device

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Quick Facts
Patent No.
US 8,988,641
App. No.
14/286,288
Granted
Mar 24, 2015
Kind
B2
Abstract

A liquid crystal display device includes a pair of substrates of which one substrate is provided with a plurality of scanning lines and a plurality of common wirings, a first insulation film covering the scanning lines, the common wirings, and the one substrate, a plurality of signal lines provided on the first insulation film, a thin film transistor provided near an intersection part of the scanning lines and the signal lines, a lower electrode formed below the first insulation film and connected to the common wirings, a second insulation film formed on surfaces of the thin film transistor, the signal lines, and the first insulation film, and an upper electrode formed on the second insulation film and having a slit, a display region in which the liquid crystal layer is driven by an electric field, and a non-display region that is formed outside the display region.

Claims (19)

1. A method for manufacturing a liquid crystal display device, comprising:

(1) covering a whole surface of a transparent substrate by a conductive layer and etching the conductive layer so as to pattern a plurality of scanning lines having a gate electrode part and a plurality of common wirings in parallel with each other;

(2) covering a whole surface of a substrate obtained in the process (1) by a transparent conductive layer and patterning lower electrodes so that the lower electrodes cover surfaces of the common wirings disposed between the lower electrodes and extend over lateral surfaces of the common wirings, on positions corresponding to respective pixels;

(3) covering a whole surface of a substrate obtained in the process (2) by a first insulation film;

(4) covering a whole surface of the first insulation film by a semiconductor layer and etching the semiconductor layer so as to pattern the semiconductor layer on a position corresponding to a gate electrode part;

(5) covering a whole surface of a substrate obtained in the process (4) by a conductive layer and etching the conductive layer so as to pattern a signal line in a direction intersecting with the scanning lines and the common wirings and pattern a drain electrode and a source electrode that is electrically connected to the signal line in each of the pixels;

(6) covering a whole surface of a substrate obtained in the process (5) by a second insulation film;

(7) forming a contact hole on the second insulation film which is positioned on the drain electrode of each of the pixels;

(8) covering a whole surface of a substrate obtained in the process (7) by a transparent conductive layer and etching the transparent conductive layer so as to pattern an upper electrode having a plurality of slits in each of the pixels, and electrically conducting the upper electrode and the drain electrode; and

(9) disposing a substrate obtained in the process (8) and a color filter substrate opposed to each other and filling a space between the substrates with liquid crystal,

wherein each of the lower electrodes covers one of the common wirings connected thereto in a manner that a step part is formed on at least one lateral surface of the one of the common wirings, and

wherein the first insulation film is formed such that when a thickness of an insulation film formed on a flat part on each of the lower electrodes is denoted as A and a thickness of an insulation film formed on a lateral surface of the step part of each of the lower electrodes is denoted as B, a step coverage of the first insulation film satisfies a relationship of B/A≧1.

2. The method according to claim 1 ,

wherein a width of the step part of each of the lower electrodes is 2.25 μm or more from the lateral surface of the common wirings.

3. The method according to claim 1 ,

wherein the step part of each of the lower electrodes is formed only near a position on which the common wirings and the signal lines intersect with each other.

4. The method according to claim 1 , further comprising:

forming a dummy pixel in a non-display region,

wherein the step part of each of the lower electrodes is formed in the dummy pixel.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072398/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 24, 2025
From: JAPAN DISPLAY EAST INC.; JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 071935/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2014
From: KINOSHITA, TAKUO; ITO, HIROYUKI
To: SONY CORPORATION
Reel/Frame 033321/0857 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2014
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 033321/0883 →