Radiation detector having a bandgap engineered absorber
View Patent ↗A radiation detector is provided that includes a photodiode having a radiation absorber with a graded multilayer structure. Each layer of the absorber is formed from a semiconductor material, such as HgCdTe. A first of the layers is formed to have a first predetermined wavelength cutoff. A second of the layers is disposed over the first layer and beneath the first surface of the absorber through which radiation is received. The second layer has a graded composition structure of the semiconductor material such that the wavelength cutoff of the second layer varies from a second predetermined wavelength cutoff to the first predetermined wavelength cutoff such that the second layer has a progressively smaller bandgap than the first bandgap of the first layer. The graded multilayer radiation absorber structure enables carriers to flow toward a conductor that is used for measuring the radiation being sensed by the radiation absorber.
1. A method of making a photodiode, the method comprising:
forming a passivation layer on a substrate;
forming a first semiconductor layer on the passivation layer, the first semiconductor layer being characterized by a first wavelength cutoff;
forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a graded composition characterized by a wavelength cutoff that varies from the first wavelength cutoff to a second wavelength cutoff; and
removing the substrate from the passivation layer, thereby exposing the passivation layer.
2. The method of claim 1 , further comprising:
forming a third semiconductor layer on the second semiconductor layer, the third semiconductor layer being characterized by the second wavelength cutoff.
3. The method of claim 1 , wherein the first semiconductor layer and the second semiconductor layer each include at least one p-type region and at least one n-type region.
4. The method of claim 1 , further comprising:
forming a via through the passivation layer, the first semiconductor layer, and the second semiconductor layer; and
forming a metal layer on a wall of the via, the metal layer being in contact with the first semiconductor layer and the second semiconductor layer.
5. The method of claim 4 , further comprising:
doping the first semiconductor layer and the second semiconductor layer, thereby forming p/n-junctions on both sides of the via.
6. The method of claim 2 , wherein the passivation layer is a first passivation layer, and wherein the method further comprises:
forming a second passivation layer on the third semiconductor layer.
7. The method of claim 6 , further comprising:
bonding the second passivation layer to a readout integrated circuit layer, the readout integrated circuit layer comprising a conductor.
8. The method of claim 7 , further comprising:
forming a metal layer that electrically couples the conductor to an n-type region of the first semiconductor layer and an n-type region of the second semiconductor layer.
9. The method of claim 8 , wherein the readout integrated circuit layer comprises an input preamp electrically coupled to the conductor.
10. The method of claim 2 , wherein the first semiconductor layer comprises a first homogenous layer of Hg x-1 Cd x Te, wherein the second semiconductor layer comprises a non-homogeneous layer of Hg x-1 Cd x Te, and wherein the third semiconductor layer comprises a second homogenous layer of Hg x-1 Cd x Te.
11. The method of claim 2 , wherein the third semiconductor layer is thinner than the first semiconductor layer.
12. The method of claim 1 , wherein the second wavelength cutoff is higher than the first wavelength cutoff.
13. The method of claim 1 , wherein the first semiconductor layer is characterized by a first bandgap, and wherein the second semiconductor layer is characterized by a bandgap that varies from the first bandgap to a second bandgap.
14. The method of claim 1 , further comprising:
forming an anti-reflection coating on the passivation layer.
15. The method of claim 1 , wherein a first thickness of the first semiconductor layer is about 0.2 microns or less.
16. The method of claim 15 , wherein a second thickness of the second semiconductor layer is about 1.8 microns or greater.
17. The method of claim 1 , wherein the passivation layer is formed on the first semiconductor layer using vapor deposition.
18. The method of claim 7 , wherein the second passivation layer is bonded to the readout integrated circuit layer using epoxy.
19. The method of claim 4 , wherein the via is formed using chemical or mechanical etching.
20. The method of claim 6 , wherein the second passivation layer has a graded composition characterized by a wavelength cutoff that varies from the second wavelength cutoff to a third wavelength cutoff, the third wavelength cutoff being smaller than the second wavelength cutoff.