Performing a cyclic redundancy checksum operation responsive to a user-level instruction
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
1. A system comprising:
a multicore processor comprising:
a cache:
a set of registers, including:
a first 32-bit register to store a first operand;
a second 32-bit register to store a second operand;
a first 64-bit register to store a third operand; and
a second 64-bit register to store a fourth operand;
a plurality of execution units to perform exclusive-OR (XOR) operations on data of a configurable size responsive to instructions of an instruction set architecture (ISA) for the processor, the plurality of execution units including:
a first execution unit coupled with the first and the second 32-bit registers to perform a first XOR operation on the first and the second operands and to store a result of the first XOR operation in a first destination register responsive to a first instruction of the ISA; and
a second execution unit coupled with the first and the second 64-bit registers to perform a second XOR operation on the third and the fourth operands and to store a result of the second XOR operation in a second destination register responsive to a second instruction of the ISA;
an execution unit coupled with the set of registers to perform a 32-bit cyclic redundancy check (CRC32) operation on a fifth operand and a sixth operand that are to be stored in registers of the set of registers and to store a result of the CRC32 operation in a destination register of the set of registers responsive to a CRC32 instruction of the ISA; and
a memory controller;
a memory coupled with the memory controller;
a graphics engine;
an audio device coupled with the processor; and
a communication device coupled with the processor.
2. The system of claim 1 , wherein the first and the second execution units are to perform the first and the second XOR operations in the same number of cycles.
3. The system of claim 1 , wherein the first destination register comprises the first 32-bit register.
4. The system of claim 1 , wherein the first destination register comprises the second 32-bit register.
5. The system of claim 1 , wherein the second destination register comprises the first 64-bit register.
6. The system of claim 1 , wherein the second destination register comprises the second 64-bit register.
7. A system comprising:
a main memory;
a data storage device;
an audio input/output (I/O) device;
a communication device;
a memory controller coupled to the main memory;
a graphics engine; and
a multicore processor coupled to the memory controller, the graphics engine, the data storage device, the audio I/O device, and the communication device, the multicore processor comprising a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general purpose registers; and
a plurality of execution units, including a store data unit, an integer execution unit, and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises logic to:
perform a cyclic redundancy check (CRC) operation in response to one or more CRC32 instructions executed in a 32-bit mode of operation or a 64-bit mode of operation, wherein the logic is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, and 32-bits, and wherein the one or more CRC32 instructions are to indicate the data size to be used.
8. The system of claim 7 , wherein the variable number of data sizes further comprises a data size of 64-bits in the 64-bit mode of operation.
9. The system of claim 7 , wherein at least one the plurality of execution units is a floating point unit.
10. The system of claim 7 , wherein the at least one of the cores further comprises an address generation unit.