Crystallization method of thin film transistor, thin film transistor array panel and manufacturing method for thin film transistor array panel
View Patent ↗Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
1. A thin film transistor array panel, comprising:
a substrate;
a gate line disposed on the substrate and comprising a gate electrode;
a gate insulating layer disposed on the gate line;
a semiconductor layer disposed on the gate insulating layer and comprising a first region and a second region;
a data line disposed on the semiconductor layer and crossing the gate line;
a source electrode connected to the data line;
a drain electrode facing the source electrode; and
a passivation layer disposed on the data line, the source electrode, and the drain electrode,
wherein the first region comprises crystalline silicon and the second region comprises amorphous silicon,
wherein the first region is disposed to correspond to the channel region of a thin film transistor and the second region is disposed around the first region, and
wherein a crystalline silicon portion of the first region of the semiconductor layer comprises the channel region and has an area larger than the channel region, and
wherein the second region of the semiconductor layer comprises portions of the semiconductor layer that are not in the first region.
2. The thin film transistor array panel of claim 1 , wherein:
an area of the first region is no more than three times an area of the channel region.
3. The thin film transistor array panel of claim 2 , wherein:
the first region comprises an upper region and a lower region and
a grain size of crystalline silicon in the upper region is different from a grain size of crystalline silicon in the lower region.
4. The thin film transistor array panel of claim 1 , wherein:
side walls of the data line, the source electrode, and the drain electrode are arranged to be substantially the same as side walls of the semiconductor layer therebelow except for in the channel region.
5. The thin film transistor array panel of claim 1 , further comprising:
an etch prevention layer disposed between the channel region of the semiconductor layer and the passivation layer.
6. The thin film transistor of claim 1 , further comprising an etch prevention layer disposed directly on the first region and in a gap between the source and drain electrodes.
7. The thin film transistor array panel of claim 6 , further comprising:
an insulating layer disposed between a periphery of the semiconductor layer and at least one of the source and drain electrodes; and
an ohmic contact layer disposed between the etch prevention layer and the insulating layer,
wherein the ohmic contact layer is disposed between the semiconductor layer and at least one of the source and drain electrodes.
8. A thin film transistor array panel, comprising:
a substrate;
a gate line disposed on the substrate and comprising a gate electrode;
a gate insulating layer disposed on the gate line;
a semiconductor layer disposed on the gate insulating layer and comprising a first region and a second region;
a data line disposed on the semiconductor layer and crossing the gate line;
a source electrode connected to the data line;
a drain electrode facing the source electrode; and
an insulating layer disposed between a periphery of the semiconductor layer and at least one of the source and drain electrodes;
an ohmic contact layer disposed between an etch prevention layer and the insulating layer; and
a passivation layer disposed on the data line, the source electrode, and the drain electrode;
an etch prevention layer disposed directly on the first region and in the gap between the source and drain electrodes; and
an ohmic contact layer disposed between an etch prevention layer and the insulating layer,
wherein the first region comprises crystalline silicon and the second region comprises amorphous silicon, and
wherein the first region is disposed to correspond to the channel region of a thin film transistor and the second region is disposed around the first region.
9. The thin film transistor array panel of claim 8 , wherein:
the ohmic contact layer is disposed between the semiconductor layer and at least one of the source and drain electrodes.
10. A thin film transistor array panel, comprising:
a substrate;
a gate line disposed on the substrate and comprising a gate electrode;
a gate insulating layer disposed on the gate line;
a semiconductor layer disposed on the gate insulating layer and comprising a first region and a second region;
a data line disposed on the semiconductor layer and crossing the gate line;
a source electrode connected to the data line;
a drain electrode facing the source electrode;
a passivation layer disposed on the data line, the source electrode, and the drain electrode;
an etch prevention layer disposed directly on the first region and in a gap between the source and drain electrodes;
an insulating layer disposed between a periphery of the semiconductor layer and at least one of the source and drain electrodes; and
an ohmic contact layer disposed between the etch prevention layer and the insulating layer,
wherein the first region comprises crystalline silicon and the second region comprises amorphous silicon,
wherein the first region is disposed to correspond to the channel region of a thin film transistor and the second region is disposed around the first region, and
wherein the first region of the semiconductor layer comprises the channel region and has an area larger than the channel region, and the second region of the semiconductor layer comprises portions of the semiconductor layer that are not in the first region; and
wherein the ohmic contact layer is disposed between the semiconductor layer and at least one of the source and drain electrodes.