IP Library Granted Patent US 9,208,077
Granted Patent B1
US 9,208,077 · App. 14/291,127 · Granted Dec 8, 2015

Forced map entry flush to prevent return of old data

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Quick Facts
Patent No.
US 9,208,077
App. No.
14/291,127
Granted
Dec 8, 2015
Kind
B1
Abstract

A data storage device flushes newly written data in response to certain events such that, when the device has acknowledged newly written data, the device cannot return old data of the referenced logical block address to the host in any case. If the data of the logical block address has been corrupted, the device returns an uncorrectable error, not old data. A “force map entry flush” flushes modified map entries to NAND when an upper page is programmed. After a power failure and restoration, a storage device is able to analysis map entries to determine whether there is some host data in the uncorrectable die, then prevent return of old data to a host.

Claims (84)

1. A computer apparatus comprising:

a processor;

memory connected to the processor; and

a data storage device comprising multi-level cell NAND,

wherein the processor is configured to:

receive a data write request to write data corresponding to a logical block address to the data storage device;

determine that one or more map entries corresponding to one or more lower pages in the data storage device are currently stored in the memory;

determine that the data will be written to an upper page corresponding to a lower page in the one or more map entries;

flush the one or more map entries to the data storage device;

write the data to one or more pages in the data storage device; and

write a map entry in the memory associating the one or more pages with a logical block address.

2. The computer apparatus of claim 1 , wherein each of the one or more map entries comprises a timestamp corresponding to a time when corresponding data was written to the data storage device.

3. The computer apparatus of claim 1 , wherein the processor is further configured to:

detect a power loss during a write operation;

identify one or more pages corrupted during the write operation; and

identify a last page written prior to an earliest corrupted page in the one or more pages.

4. The computer apparatus of claim 3 , wherein the processor is further configured to:

determine a last timestamp associated with the last page; and

scan a data structure comprising map entries to identify one or more map entries having a substantially similar timestamp to the last timestamp.

5. The computer apparatus of claim 4 , wherein the processor is further configured to:

scan the data structure to identify one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation;

set a flag in the one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation indicating that all map entries associated with the logical block address are corrupted.

6. The computer apparatus of claim 5 , wherein the processor is further configured to:

receive a read request for data in the logical block address;

search one or more map entries in the data structure to find a map entry associated with the logical block address; and

return a corrupt status upon identifying the flag.

7. The computer apparatus of claim 1 , wherein the processor is further configured to:

receive a read request for data in a logical block address;

search one or more map entries in a data structure of map entries associating logical block addresses with pages in the data storage device to find a map entry associated with the logical block address;

identify a flag indicating that any map entries associated with the logical block address are corrupted; and

return a corrupt status upon identifying the flag.

8. A method comprising:

receiving a data write request to write data corresponding to a logical block address to the data storage device;

determining that one or more map entries corresponding to one or more lower pages in the data storage device are currently stored in the memory;

determining that the data will be written to an upper page corresponding to a lower page in the one or more map entries;

flushing the one or more map entries to the data storage device;

writing the data to one or more pages in the data storage device; and

writing a map entry in the memory associating the one or more pages with a logical block address.

9. The method of claim 8 , wherein each of the one or more map entries comprises a timestamp corresponding to a time when corresponding data was written to the data storage device.

10. The method of claim 8 , further comprising:

detecting a power loss during a write operation;

identifying one or more pages corrupted during the write operation; and

identifying a last page written prior to an earliest corrupted page in the one or more pages.

11. The method of claim 10 , further comprising:

determining a last timestamp associated with the last page; and

scanning a data structure comprising map entries to identify one or more map entries having a substantially similar timestamp to the last timestamp.

12. The method of claim 11 , further comprising:

scanning the data structure to identify one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation;

setting a flag in the one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation indicating that all map entries associated with the logical block address are corrupted.

13. The method of claim 12 , further comprising:

receiving a read request for data in the logical block address;

searching one or more map entries in the data structure to find a map entry associated with the logical block address; and

returning a corrupt status upon identifying the flag.

14. A multi-level cell data storage system comprising:

a processor;

memory connected to the processor; and

computer executable program code,

wherein the computer executable program code configures the processor to:

receive a data write request to write data corresponding to a logical block address to the data storage device;

determine that one or more map entries corresponding to one or more lower pages in the data storage device are currently stored in the memory;

determine that the data will be written to an upper page corresponding to a lower page in the one or more map entries;

flush the one or more map entries to the data storage device;

write the data to one or more pages in the data storage device; and

write a map entry in the memory associating the one or more pages with a logical block address.

15. The multi-level cell data storage system of claim 14 , wherein each of the one or more map entries comprises a timestamp corresponding to a time when corresponding data was written to the data storage device.

16. The multi-level cell data storage system of claim 14 , wherein the processor is further configured to:

detect a power loss during a write operation;

identify one or more pages corrupted during the write operation; and

identify a last page written prior to an earliest corrupted page in the one or more pages.

17. The multi-level cell data storage system of claim 16 , wherein the processor is further configured to:

determine a last timestamp associated with the last page; and

scan a data structure comprising map entries to identify one or more map entries having a substantially similar timestamp to the last timestamp.

18. The multi-level cell data storage system of claim 17 , wherein the processor is further configured to:

scan the data structure to identify one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation;

set a flag in the one or more map entries having a timestamp subsequent to the last timestamp, and corresponding to a logical block address associated with at least one of the one or more pages corrupted during the write operation indicating that all map entries associated with the logical block address are corrupted.

19. The multi-level cell data storage system of claim 18 , wherein the processor is further configured to:

receive a read request for data in the logical block address;

search one or more map entries in the data structure to find a map entry associated with the logical block address; and

return a corrupt status upon identifying the flag.

20. The multi-level cell data storage system of claim 14 , wherein the processor is further configured to:

receive a read request for data in a logical block address;

search one or more map entries in a data structure of map entries associating logical block addresses with pages in the data storage device to find a map entry associated with the logical block address;

identify a flag indicating that any map entries associated with the logical block address are corrupted; and

return a corrupt status upon identifying the flag.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2014
From: MA, LI ZHAO; YUAN, RONG; XU, PENG
To: LSI CORPORATION
Reel/Frame 032993/0826 →