SCALABLE EFFICIENT FRAMING FOR DIGITAL SIGNALS

1 . A network element comprising:

a port configured to couple to a transmission medium and to receive a signal comprising data bits; and

a frame alignment detector comprising:

a frame-detection shifting circuit configured to:

receive the data bits of the signal;

insert the data bits into a first-in-first-out (FIFO) queue; and

select a set of the data bits corresponding to offsets of framing bits in a serialized data format;

a framing decoder communicatively coupled to the frame-detection shifting circuit, the framing decoder configured to:

compare the set of bits to expected values of the framing bits;

determine whether the set of bits matches the expected values; and

if the set of bits matches the expected values, indicating that a frame was detected.

2 . The network element of claim 1 , wherein the frame-detection shifting circuit comprises:

at least one shifter configured to operate as a FIFO queue; and

at least one flip-flop configured to select the set of data bits corresponding to the offsets.

3 . The network element of claim 1 , wherein the frame-detection shifting circuit comprises:

a shift register configured to operate as a FIFO queue; and

at least one internal tap of the shift register configured to select the set of data bits corresponding to the offsets.

4 . The network element of claim 1 , wherein the frame alignment detector further comprises a frame bit counter configured to count the number of data bits received since the most recent frame was detected.

5 . The network element of claim 1 , the frame alignment detector further comprising:

a selector configured to select data bits from a plurality of input lines; and

a multiplexer coupled communicatively coupled to the selector, the multiplexer configured to serialize the data bits onto a multiplexer output line; and

wherein receiving data bits comprises receiving data bits from the multiplexer output line.

6 . The network element of claim 5 , wherein the serialized data format is a DS3 format and the offsets are offsets of a DS3 format times the number of input lines in the plurality of input lines.

7 . The network element of claim 5 , wherein the serialized data format is a SONET/SDH format and the offsets are offsets of a SONET/SDH format times the number of input lines in the plurality of input lines.

8 . The network element of claim 5 , wherein the serialized data format is an OTN format and the offsets are offsets of an OTN format times the number of input lines in the plurality of input lines.

9 . The network element of claim 1 , wherein the frame-detection shifting circuit comprises a logic block on an application-specific integrated circuit (ASIC).

10 . The network element of claim 1 , wherein the frame-detection shifting circuit comprises a logic block on a field-programmable gate array (FPGA).

11 . A method for detecting framing bits in a digital data stream comprising:

receiving a data bit;

inserting the data bit into a frame-detection shifting circuit configured to operate as a first-in-first-out (FIFO) queue;

selecting, from the frame-detection shifting circuit. a set of bits corresponding to offsets of framing bits in a serialized data format;

comparing the set of bits to expected values of the framing bits;

determining whether the set of bits matches the expected values;

if the set of bits matches the expected values, indicating that a frame was detected;

shifting the frame-detection shifting circuit by one bit position; and

repeating the receiving, inserting, selecting, comparing, determining, indicating, and shifting.

12 . The method of claim 11 , wherein the frame-detection shifting circuit comprises:

at least one shifter configured to operate as a FIFO queue; and

at least one flip-flop configured to select the set of data bits corresponding to the offsets.

13 . The method of claim 11 , wherein the frame-detection shifting circuit comprises:

a shift register configured to operate as a FIFO queue; and

at least one internal tap of the shift register configured to select the set of data bits corresponding to the offsets.

14 . The method of claim 11 , further comprising counting the number of data bits received since the most recent frame was detected.

15 . The method of claim 11 , wherein receiving a data bit comprises receiving a data bit from one of a plurality of input lines.

16 . The method of claim 11 , wherein the serialized data format is a DS3 format and the offsets are offsets of a DS3 format times the number of input lines in the plurality of input lines.

17 . The method of claim 11 , wherein the serialized data format is a SONET/SDH format and the offsets are offsets of a SONET/SDH format times the number of input lines in the plurality of input lines.

18 . The method of claim 11 , wherein the serialized data format is an OTN format and the offsets are offsets of an OTN format times the number of input lines in the plurality of input lines.

19 . The method of claim 11 , wherein the frame-detection shifting circuit comprises a logic block on an application-specific integrated circuit (ASIC).

20 . The method of claim 11 , wherein the frame-detection shifting circuit comprises a logic block on a field-programmable gate array (FPGA).