IP Library Granted Patent US 9,612,931
Granted Patent B2
US 9,612,931 · App. 14/295,607 · Granted Apr 4, 2017

System and method for synchronously controlling LED on multiple control modules based on a register synchronized with synchronous packets

Inventors: Akihiro Umezawa (Tokyo, JP); Nobuo Yagi (Tokyo, JP); Kazuki Sato (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F11/325G05B2219/31213G06F11/3031G06F11/3058G06F13/4243G06F17/5027G06F17/5054H04N13/0051H04N13/0296H04N21/4302H04N21/633H04N21/64746
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,612,931
App. No.
14/295,607
Granted
Apr 4, 2017
Kind
B2
Abstract

In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

Claims (32)

1. An information processing system, the system comprising:

a plurality of information processing devices; and

a system device control module communicatively coupled to each of the plurality of information processing devices;

wherein each information processing device includes:

one or more processors,

a light emitting diode (LED),

a clock generation circuit,

a control device, wherein the control device includes a synchronous register, and

a sensor, wherein the sensor includes at least a temperature sensor or a power source sensor;

wherein each control device:

determines the state of a control signal based on a detection of an error by the sensor,

stores the state of a control signal in the synchronous register based on the clock generation circuit,

receives one or more synchronous packets from the plurality of information processing devices,

synchronizes the synchronous register based on the received one or more synchronous packets, and

synchronously flashes the LED based on the synchronous register.

2. The information processing system according to claim 1 , wherein the control device is a Field Programmable Gate Array (FPGA).

3. The information processing system according to claim 1 , wherein the state of the control signal is further based on a signal for power saving control.

4. The information processing system according to claim 1 , wherein each of the plurality of information processing devices further include a power source device, and

wherein the state of the control signal is further based on a signal for controlling the power source of each information processing device.

5. The information processing system according to claim 1 , wherein each of the plurality of information processing devices further include a Redundant Array of Independent Disks (RAID) controller and a storage device controlled by the RAID controller,

and wherein the state of the control signal is further based on a control signal from the RAID controller.

6. The information processing system according to claim 1 , wherein each of the plurality of information processing devices further include a Local Area Network (LAN) controller that outputs a power-on signal, and the control signal is the power-on signal.

7. A synchronous control method, the method comprising the steps of:

storing, by a particular information processing device from a plurality of information processing devices, a state of a control signal in a synchronous register based on a detection of an error by a particular sensor of the particular information processing device, wherein each of the plurality of information processing devices includes:

one or more processors,

a light emitting diode (LED),

a clock generation circuit,

a control device, wherein the control device includes a synchronous register, and

the sensor, wherein the sensor includes at least a temperature sensor or a power source sensor;

receiving, by the particular information processing device, one or more synchronous packets from the plurality of information processing devices;

synchronizing, by the particular information processing device, the synchronous register of the particular information processing device, based on the one or more synchronous packets, and

synchronously flashing, by the particular information processing device, the LED of the particular information processing device based on the synchronous register.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2014
From: UMEZAWA, AKIHIRO; YAGI, NOBUO; SATO, KAZUKI
To: HITACHI, LTD.
Reel/Frame 033065/0740 →
Priority Claims (1)
JP 2013-118914 · Jun 5, 2013 · national
Continuity (1)
Related Publication 20140365629A1 · Dec 11, 2014