Method and apparatus for cancellation of interference from a spread spectrum phase lock loop
View Patent ↗Systems and methods for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). The system and method uses a sinusoidal spreading signal to spread the output of a SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.
1. A receiver comprising:
a) a receiver front end having an output;
b) an undesirable signals mitigation module having an input coupled to the output of the receiver front end and comprising a tunable notch filter having a control input;
c) a digital core and peripheral interface/clock module having an input; and
d) a spread spectrum phase lock loop comprising:
i) a frequency source having an output;
ii) a phase detector having a first and second input, the first input coupled to the output of the frequency source and having an output;
iii) a low pass filter having an input coupled to the output of the phase detector and having an output;
iv) a VCO having an input coupled to the low pass filter and having an output;
v) a divider having a first and second input, the first input coupled to the output of the VCO, and having an output coupled to the second input to the phase detector; and
vi) a sinusoidal wave generator having a first and second output, the first output coupled to the input of the divider and the second output coupled to the control input of the tunable notch filter.
2. The receiver of claim 1 , wherein the tunable notch filter is implemented digitally within a DSP.
3. The receiver of claim 1 , wherein the first output of the sinusoidal wave generator is synchronized to a frequency source and the tunable notch filter comprises a clock synchronized to the frequency source, the clock being used to control the tracking of the tunable notch filter and being controlled by the output of the sinusoidal wave generator.
4. The receiver of claim 1 , wherein the output from the sinusoidal wave generator is a series of digital values that each represent the amplitude of a sinusoidal waveform.
5. The receiver of claim 1 , wherein the second output of the sinusoidal wave generator provides information indicating the frequency of a signal output from the first output of the sinusoidal wave generator.
6. The receiver of claim 5 , wherein the information indicating the frequency of the sinusoidal wave is used to tune the frequency of the tunable notch filter.
7. The receiver of claim 6 , wherein the phase of the output signal from the phase lock loop is synchronized with the tuning of the tunable notch filter.
8. The receiver of claim 7 , wherein the synchronization is accomplished by aligning a spurious signal to be cancelled with the frequency of the notch in the tunable notch filter.
9. A system on a chip (SoC) comprising:
a) a digital to analog converter (DAC);
b) an analog to digital converter (ADC);
c) an undesirable signals mitigation module comprising a tunable notch filter, the undesirable signals mitigation module coupled to the DAC and ADC;
d) a digital core coupled to the DSP; and
e) a spread spectrum phase lock loop (SS PLL) coupled to the DSP, the SS PLL comprising
i) a frequency source having an output;
ii) a phase detector having a first and second input, the first input coupled to the output of the frequency source and having an output;
iii) a low pass filter having an input coupled to the output of the phase detector and having an output;
iv) a VCO having an input coupled to the low pass filter and having an output coupled to the digital core;
v) a divider having a first and second input, the first input coupled to the output of the VCO, and having an output coupled to the second input to the phase detector; and
vi) a sinusoidal wave generator having a first and second output, the first output coupled to the input of the divider and the second output coupled to the control input of the tunable notch filter.
10. A method for cancelling interference created by a phase lock loop comprising:
a) generating a frequency;
b) comparing the phase of the generated frequency to the output of a divider;
c) low pass filtering the compared phase;
d) controlling the frequency of a voltage controlled oscillator (VCO) with the filtered phase comparison;
e) providing the output of the VCO to the divider to be divided by a value that varies as a sinusoid; and
f) controlling the frequency of a notch in a notch filter using information regarding the frequency and phase of the sinusoid.
11. The method of claim 10 , further comprising filtering though the notch filter a signal having interference generated by leakage of the output of the phase lock loop.