IP Library Granted Patent US 9,645,954
Granted Patent B2
US 9,645,954 · App. 14/297,485 · Granted May 9, 2017

Embedded microcontroller and buses

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,645,954
App. No.
14/297,485
Granted
May 9, 2017
Kind
B2
Abstract

A system can include a power supply unit; a processor; memory operatively coupled to the processor; a chipset operatively coupled to the processor; diagnostic information memory; and a microcontroller operatively coupled to the chipset via a first diagnostic data transfer bus and the microcontroller operatively coupled to the power supply unit and to the diagnostic information memory via a second diagnostic data transfer bus.

Claims (40)

1. A system comprising:

a power supply unit;

a processor;

memory operatively coupled to the processor;

a chipset operatively coupled to the processor;

diagnostic information memory;

a port hub operatively coupled to the diagnostic information memory;

a microcontroller operatively coupled to the chipset via a first diagnostic data transfer bus and the microcontroller operatively coupled to the power supply unit and to the diagnostic information memory via a second diagnostic data transfer bus; and

sensors operatively coupled to the microcontroller,

wherein the microcontroller analyzes at least a portion of sensor data to generate a thermal management status for storage in the diagnostic information memory and for output via the port hub, and

wherein the microcontroller analyzes at least a portion of diagnostic data to generate a diagnostic result for storage in the diagnostic information memory and for output via the port hub.

2. The system of claim 1 wherein the microcontroller comprises an embedded microcontroller of a super I/O.

3. The system of claim 1 wherein the second diagnostic data transfer bus comprises an I2C bus.

4. The system of claim 1 wherein the second diagnostic data transfer bus comprises a SMBus bus.

5. The system of claim 1 wherein the diagnostic information memory comprises EEPROM.

6. The system of claim 1 wherein the diagnostic information memory comprises flash memory.

7. The system of claim 1 wherein the second diagnostic data transfer bus operatively couples the port hub and the diagnostic information memory.

8. The system of claim 1 wherein the diagnostic result is based at least in part on a status of the power supply unit and based at least in part on a status of the processor.

9. A method comprising:

sensing information associated with one or more components of a computer;

receiving diagnostic information via a diagnostic data transfer bus wherein the diagnostic information pertains to a power supply unit operatively coupled to the diagnostic data transfer bus;

analyzing at least a portion of the diagnostic information to generate a diagnostic result that pertains to the power supply unit;

analyzing at least a portion of the sensed information to generate a thermal management status that pertains to operation of the computer;

transferring the diagnostic result to memory via the diagnostic data transfer bus;

transferring the thermal management status to the memory via the diagnostic data transfer bus; and

transferring the diagnostic result, the thermal management status or the diagnostic result and the thermal management status from the memory to a port hub via the diagnostic data transfer bus.

10. The method of claim 9 wherein the analyzing comprises executing instructions on a microcontroller embedded in a Super I/O.

11. The method of claim 9 wherein the port hub comprises a USB port hub.

12. The method of claim 9 further comprising switching a switch associated with a port associated with the port hub and transferring the diagnostic result to the port in a manner that bypasses the port hub.

13. The method of claim 12 wherein the switching comprises issuing a switch signal from a microcontroller embedded in a Super I/O to the switch.

14. The method of claim 9 further comprising receiving from a chipset, diagnostic information that pertains to a processor operatively coupled to the chipset.

15. The method of claim 14 further comprising analyzing the diagnostic information that pertains to the processor to generate a diagnostic result and transferring the diagnostic result to the memory via the diagnostic data transfer bus.

16. A system comprising:

a Super I/O that comprises a first data transfer interface operatively coupled to a power supply unit and a second data transfer interface operatively coupled to at least one sensor;

a memory unit that comprises memory and a data transfer interface;

a bus that operatively couples the first data transfer interface of the Super I/O to the data transfer interface of the memory unit;

a port hub that comprises a data transfer interface that is operatively coupled to the bus; and

a microcontroller embedded in the Super I/O that comprises circuitry to receive data via the first and second data transfer interfaces of the Super I/O, to analyze at least a portion of the data to generate a result, and to transfer the result to the memory unit via the bus for output via the port hub, wherein the result comprises one of a thermal management status based at least in part on sensor information and a diagnostic result based at least in part on power supply information.

17. The system of claim 16 further comprising a port switch that switches a connection state of a port operatively coupled to the port hub.

18. The system of claim 17 wherein the microcontroller embedded in the Super I/O comprises circuitry to transfer information to the port hub, circuitry to control the connection state of the port switch, and circuitry to transfer information from the Super I/O to the port in a manner that bypasses the port hub.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: LENOVO PC INTERNATIONAL LIMITED
To: LENOVO SWITZERLAND INTERNATIONAL GMBH
Reel/Frame 069870/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2019
From: LENOVO (SINGAPORE) PTE. LTD.
To: LENOVO PC INTERNATIONAL LIMITED
Reel/Frame 049693/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2014
From: PAMLEY, MARC RICHARD; ALI, OMAR ALI; PAINTER, ALAN LADD; YOUNG, BRYAN L.; KEOWN, JR., WILLIAM FRED
To: LENOVO (SINGAPORE) PTE. LTD.
Reel/Frame 033127/0098 →