System and method for determining power loads
A computer-implemented method enables determining an input power load for a multi voltage rail subsystem in an electronic device such as an information handing system. The method comprises determining a first output power value from a first voltage regulator and a second output power value from a second voltage regulator. A first input power value to the first voltage regulator is determined based at least partially on the first output power value and a second input power value to the second voltage regulator is determined based at least partially on the second output power value. An offset power value is calculated based on the first input power value and the second input power value. A total input power value is calculated based on the offset power value and a third input power value. The total input power value is transmitted to a processor.
1. A computer implemented method of determining a power load for at least one subsystem in an electronic device such as an information handling system, the method comprising:
retrieving a first output power value from a first voltage regulator (VR) and a second output power value from a second voltage regulator;
determining, by one of a VR controller and a board management module (BMC), both (i) a first input power value to the first voltage regulator based at least partially on the first output power value and (ii) a second input power value to the second voltage regulator based at least partially on the second output power value, wherein the determining includes referencing one of an input power table associated with an identified processor type and a power efficiency table;
calculating, by the VR controller, an offset power value based on the first input power value and the second input power value;
calculating, by the VR controller, a total input power value based on the offset power value and a third input power value to a third voltage regulator; and
transmitting, by the VR controller, the total input power value to a processor of the electronic device, wherein the processor utilizes the total input power value to determine if the processor can support operation at higher frequencies, including at turbo states, or at higher processing speeds.
2. The method of claim 1 , further comprising:
identifying, via a board management controller, a processor type;
retrieving an input power table associated with the identified processor type;
completing the determining of the first input power value based from the first output power value by utilizing the input power table;
completing the determining of the second input power value from the second output power value by utilizing the input power table;
transmitting the first input power value and the second input power value from the board management controller to a third voltage regulator; and
storing the first input power value and the second input power value to an offset register of the third voltage regulator.
3. The method of claim 1 , further comprising:
triggering, via a board management controller, a processor stress test;
determining, via the board management controller, the first output power value and the second output power value during the processor stress test;
retrieving a power efficiency table;
completing the determining of the first input power value from the first output power value by utilizing the power efficiency table;
completing the determining of the second input power value from the second output power value by utilizing the power efficiency table;
transmitting the first input power value and the second input power value from the board management controller to a third voltage regulator; and
storing the first input power value and the second input power value to an offset register of the third voltage regulator.
4. The method of claim 1 , further comprising:
determining, via a board management controller, the first output power value and the second output power value during operation of the processor;
retrieving a power efficiency table;
completing the determining of the first input power value from the first output power value by utilizing the power efficiency table;
completing the determining of the second input power value from the second output power value by utilizing the power efficiency table;
transmitting the first input power value and the second input power value from the board management controller to a third voltage regulator; and
storing the first input power value and the second input power value to an offset register of the third voltage regulator.
5. The method of claim 1 , wherein determining the first output power value from the first voltage regulator and the second output power value from the second voltage regulator is based at least partially on a third voltage regulator polling the first voltage regulator for the first output power value and the second voltage regulator for the second output power.
6. The method of claim 5 , further comprising:
retrieving, via the third voltage regulator, a power efficiency table;
completing the determining, via the third voltage regulator, of the first input power value from the first output power value by utilizing the power efficiency table;
completing the determining, via the third voltage regulator, of the second input power value from the second output power value by utilizing the power efficiency table;
calculating, via the third voltage regulator, the offset power value based on the first input power value and the second input power value; and
calculating, via the third voltage regulator, the total input power value based on the offset power value and the third input power value.
7. The method of claim 1 , wherein determining the first output power value from the first voltage regulator and the second output power value from the second voltage regulator comprises a micro-controller retrieving the first output power value from the first voltage regulator and the second output power value from the second voltage regulator.
8. The method of claim 7 , further comprising:
retrieving, via the micro-controller, a power efficiency table;
completing the determining, via the micro-controller, of the first input power value from the first output power value by utilizing the power efficiency table;
completing the determining, via the micro-controller, of the second input power value from the second output power value by utilizing the power efficiency table; and
transmitting the first input power value and the second input power value from the micro-controller to a third voltage regulator.
9. The method of claim 1 , wherein the first input power value is associated with power delivered to a memory controller power terminal of the processor, the second input power value is associated with power delivered to a math coprocessor power terminal of the processor and the third input power value is associated with power delivered to a primary input power terminal of the processor.
10. A power control system comprising:
a power subsystem configured to be coupled to and supply power to a processor, the power subsystem including a first voltage regulator, a second voltage regulator, a third voltage regulator and a board management controller communicatively coupled to the first, second and third voltage regulators, the board management controller having power management firmware executing thereon that configures the board management controller (BMC) to:
retrieve a first output power value from a first voltage regulator (VR) and a second output power value from a second voltage regulator;
determine both (i) a first input power value to the first voltage regulator based at least partially on the first output power value and (ii) a second input power value to the second voltage regulator based at least partially on the second output power value, wherein the determining includes referencing one of an input power table associated with an identified processor type and a power efficiency table; and
transmit the first input power value and the second input power value from the board management controller to the third voltage regulator; and
a VR controller configured to:
calculate an offset power value based on the first input power value and the second input power value;
calculate a total input power value based on the offset power value and a third input power value to a third voltage regulator; and
transmit the total input power value to a processor of the electronic device, wherein the processor utilizes the total input power value to determine if the processor can support operation at higher frequencies, including at turbo states, or at higher processing speeds.
11. The power control system of claim 10 , wherein the power management firmware further configures the board management controller to:
identify a processor type;
retrieve an input power table associated with the identified processor type;
complete the determining of the first input power value utilizing the first output power value and the input power table; and
complete the determining of the second input power value utilizing the second output power value and the input power table.
12. The power control system of claim 10 , wherein the power management firmware further configures the board management controller to:
trigger a processor stress test;
determine the first output power value and the second output power value during the processor stress test;
retrieve a power efficiency table;
complete the determining of the first input power value using the first output power value and the power efficiency table; and
complete the determining of the second input power value using the second output power value and the power efficiency table.
13. The power control system of claim 10 , wherein the power management firmware further configures the board management controller to:
determine the first output power value and the second output power value during operation of the processor;
retrieve a power efficiency table;
complete the determining of the first input power value using the first output power value and the power efficiency table; and
complete the determining of the second input power value using the second output power value and the power efficiency table.
14. The power control system of claim 10 , wherein the first input power value is associated with power delivered to a memory controller power terminal of the processor, the second input power value is associated with power delivered to a math coprocessor power terminal of the processor and the third input power value is associated with power delivered to a primary input power terminal of the processor.
15. A power control system comprising:
a power subsystem configured to be coupled to and supply power to a processor, the power subsystem including a first voltage regulator, a second voltage regulator, a third voltage regulator and a voltage regulator controller having power management firmware executing thereon that configures the voltage regulator controller to:
determine a first output power value from the first voltage regulator and a second output power value from the second voltage regulator;
retrieve a power efficiency table;
determine a first input power value to the first voltage regulator using the first output power value and the power efficiency table; and
determine a second input power value to the second voltage regulator using the second output power value and the power efficiency table;
calculate an offset power value based on the first input power value and the second input power value;
calculate a total input power value based on the offset power value and a third input power value to a third voltage regulator; and
transmit, by the VR controller, the total input power value to the processor, wherein the processor utilizes the total input power value to determine if the processor can support operation at higher frequencies, including at turbo states, or at higher processing speeds.
16. The power control system of claim 15 , wherein the power management firmware further configures the voltage regulator controller to:
store the offset power value to an offset power register.
17. The power control system of claim 15 , wherein the first input power value is associated with power delivered to a memory controller power terminal of the processor, the second input power value is associated with power delivered to a math coprocessor power terminal of the processor and the third input power value is associated with power delivered to a primary input power terminal of the processor.
18. An information handling system (IHS) comprising:
at least one processor;
a power subsystem communicatively coupled to the processor, the power subsystem supplying power to the at least one processor, the power subsystem including a first voltage regulator, a second voltage regulator, a third voltage regulator and a board management controller communicatively coupled to the first, second and third voltage regulators, the board management controller having power management firmware executing thereon that configures the board management controller to:
determine a first output power value from the first voltage regulator and a second output power value from the second voltage regulator;
determine both (i) a first input power value to the first voltage regulator based at least partially on the first output power value and (ii) a second input power value to the second voltage regulator based at least partially on the second output power value, wherein the determining includes referencing one of an input power table associated with an identified processor type and a power efficiency table;
transmit the first input power value and the second input power value from the board management controller to a VR controller of the third voltage regulator; and
the power subsystem comprising the VR controller, which has additional power management firmware executing thereon that configures the VR controller to:
calculate, via the VR controller, an offset power value based on the first input power value and the second input power value;
calculate, by the VR controller, a total input power value based on the offset power value and a third input power value of the third voltage regulator; and
transmitting, by the VR controller, the total input power value to a processor of the electronic device, wherein the processor utilizes the total input power value to determine if the processor can support operation at higher frequencies, including at turbo states, or at higher processing speeds.
19. The information handling system of claim 18 , wherein the power management firmware further configures the board management controller to:
identify a processor type;
retrieve an input power table associated with the identified processor type;
complete the determining of the first input power value using the first output power value and the input power table; and
complete the determining of the second input power value using the second output power value and the input power table.
20. The information handling system of claim 18 , wherein the power management firmware further configures the board management controller to:
trigger a processor stress test;
determine the first output power value and the second output power value during the processor stress test;
retrieve a power efficiency table;
complete the determining of the first input power value using the first output power value and the power efficiency table; and
complete the determining of the second input power value using the second output power value and the power efficiency table.
21. The information handling system of claim 18 , wherein the power management firmware further configures the board management controller to:
determine the first output power value and the second output power value during operation of the processor;
retrieve a power efficiency table;
complete the determining of the first input power value using the first output power value and the power efficiency table; and
complete the determining of the second input power value using the second output power value and the power efficiency table.
22. The information handling system of claim 18 , wherein the first input power value is associated with power delivered to a memory controller power terminal of the processor, the second input power value is associated with power delivered to a math coprocessor power terminal of the processor and the third input power value is associated with power delivered to a primary input power terminal of the processor.
23. An information handling system (IHS) comprising:
at least one processor;
a power subsystem communicatively coupled to the processor, the power subsystem supplying power to the processor, the power subsystem including a first voltage regulator, a second voltage regulator, a third voltage regulator and a voltage regulator controller communicatively coupled to the first, second and third voltage regulators, the voltage regulator controller having power management firmware executing thereon that configures the voltage regulator (VR) controller to:
determine a first output power value from the first voltage regulator and a second output power value from the second voltage regulator;
retrieve a power efficiency table;
determine a first input power value to the first voltage regulator using the first output power value and the power efficiency table;
determine a second input power value to the second voltage regulator using the second output power value and the power efficiency table;
transmit the first input power value and the second input power value from a board management controller to the VR controller of the third voltage regulator;
calculate an offset power value based on the first input power value and the second input power value;
calculate a total input power value based on the offset power value and a third input power value of the third voltage regulator; and
transmit the total input power value to a processor of the electronic device, wherein the processor utilizes the total input power value to determine if the processor can support operation at higher frequencies, including at turbo states, or at higher processing speeds.
24. The information handling system of claim 23 , wherein the power management firmware further configures the voltage regulator controller to:
store the offset power value to an offset power register.
25. The information handling system of claim 23 , wherein the first input power value is associated with power delivered to a memory controller power terminal of the processor, the second input power value is associated with power delivered to a math coprocessor power terminal of the processor and the third input power value is associated with power delivered to a primary input power terminal of the processor.