Multi-thread graphics processing system
View Patent ↗A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
1. In a graphics processing system, a method for selecting command threads for processing, the method comprising:
selecting, by an arbiter circuit implemented by the graphics processing system, command threads from among a plurality of pixel command threads and a plurality of vertex command threads, wherein the arbiter circuit selects a pixel command thread as a selected command thread and a vertex command thread as another selected command thread;
intermixing, in an order determined based on a command of the selected pixel command thread and a command of the selected vertex command thread, an execution, in an arithmetic logic unit, of commands of the selected pixel command thread with commands of the selected vertex command thread;
maintaining a first status of the selected pixel command thread, wherein the first status is used by the arbiter circuit to perform the selecting of the selected pixel command thread; and
maintaining, concurrently with the first status, a second status of the selected vertex command thread, wherein the second status is used by the arbiter circuit to perform the selecting of the selected vertex command thread.
2. The method of claim 1 , wherein the arithmetic logic unit is operatively connected to the arbiter circuit.
3. The method of claim 2 , further comprising:
executing, by the arithmetic logic unit, the commands of the selected pixel command thread to provide a first executed command thread; and
executing, by the arithmetic logic unit, the commands of the selected vertex command thread to provide a second executed command thread.
4. The method of claim 3 , further comprising:
providing the first executed command thread to a render backend circuit; and
providing the second executed command thread to a scan converter circuit.
5. The method of claim 1 , wherein the selecting of the selected pixel command thread further comprises retrieving, as the selected pixel command thread, an oldest one of the plurality of pixel command threads stored in a first reservation station.
6. The method of claim 1 , further comprising:
providing, by the arbiter circuit, the command of the selected vertex command thread to a texture engine circuit operatively connected to the arbiter circuit.
7. The method of claim 6 , further comprising:
executing, by the texture engine circuit, the command of the selected vertex command thread to provide an executed command thread.
8. The method of claim 7 , further comprising:
providing the executed command thread to a scan converter circuit.
9. The method of claim 1 , wherein the command of the selected pixel command thread is a non-executed command in the selected pixel command thread.
10. The method of claim 1 , wherein the command of the selected pixel command thread is an executed command in the selected pixel command thread.
11. The method of claim 1 , wherein:
the command of the selected pixel command thread is a non-executed command in the selected pixel command thread, and
the command of the selected vertex command thread is a non-executed command in the selected vertex command thread.
12. A graphics processing system comprising:
at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads; and
an arbiter circuit, coupled to the at least one memory device, operative to select command threads from among the plurality of pixel command threads and the plurality of vertex command threads,
wherein the arbiter circuit is operative to select a pixel command thread as a selected command thread and a vertex command thread as another selected command thread;
wherein the arbiter circuit is operative to intermix, in an order determined based on a command of the selected pixel command thread and a command of the selected vertex command thread, an execution, in an arithmetic logic unit, of commands of the selected pixel command thread with commands of the selected vertex command thread;
wherein the at least one memory device is operative to maintain a first status of the selected pixel command thread, wherein the first status is used by the arbiter circuit to perform the selecting of the selected pixel command thread; and
wherein the at least one memory device is operative to maintain, concurrently with the first status, a second status of the, selected vertex command thread, wherein the second status is used by the arbiter circuit to perform the selecting of the selected vertex command thread.
13. The graphics processing system of claim 12 , wherein the arbiter circuit is coupled to the arithmetic logic unit and is operative to provide the selected command threads to the arithmetic logic unit.
14. The graphics processing system of claim 13 , wherein the arbiter circuit is coupled to a texture engine circuit and is operative to provide the selected command threads to the texture engine circuit to execute at least one command of the selected command threads.
15. The graphics processing system of claim 12 , wherein the first portion of the at least one memory device comprises a first memory device and the second portion of the at least one memory device comprises a second memory device.
16. The graphics processing system of claim 12 , wherein the first portion and the second portion of the at least one memory device are implemented on the same die.
17. The graphics processing system of claim 12 , wherein the first status comprises a waiting on texture read to complete information.
18. The graphics processing system of claim 12 , wherein the arithmetic logic unit is operative to execute the commands of the selected pixel command thread to provide a first executed command thread and execute the commands of the selected vertex command thread to provide a second executed command thread.
19. The graphics processing system of claim 18 , further comprising:
a render backend circuit, coupled to the arithmetic logic unit, operative to receive the first executed command thread; and
a scan converter circuit, coupled to the arithmetic logic unit, operative to receive the second executed command thread.
20. The graphics processing system of claim 12 , wherein the command of the selected pixel command thread is a non-executed command in the selected pixel command thread.
21. The graphics processing system of claim 12 , wherein the command of the selected pixel command thread is an executed command in the selected pixel command thread.
22. The graphics processing system of claim 12 , wherein:
the command of the selected pixel command thread is a non-executed command in the selected pixel command thread, and
the command of the selected vertex command thread is a non-executed command in the selected vertex command thread.
23. In a graphics processing system, a method for selecting command threads for processing, the method comprising:
selecting, by an arbiter circuit implemented by the graphics processing system, a selected command thread from among a plurality of pixel command threads stored in a first portion of memory and a plurality of vertex command threads stored in a second portion of memory;
providing, by the arbiter circuit, the selected command thread to an arithmetic logic unit;
executing, in the arithmetic logic unit, a command of the selected command thread;
regardless of whether the selected command thread is a pixel command thread or a vertex command thread, selecting, by the arbiter circuit, a second selected command thread from among the plurality of pixel command threads and the plurality of vertex command threads; and
providing, by the arbiter circuit, the second selected command thread to the arithmetic logic unit,
wherein the arbiter circuit provides the command of the selected command thread to the arithmetic logic unit before a command of the second selected command thread based on a status of a texture read associated with the second selected command thread.
24. The method of claim 23 , further comprising:
updating the first portion of memory in response to executing the command of the second selected command thread if the second selected command thread is the pixel command thread; and
updating the second portion of memory in response to executing the command of the second selected command thread if the second selected command thread is the vertex command thread.
25. The method of claim 24 , further comprising:
updating the first portion of memory in response to executing the command of the selected command thread if the selected command thread is the pixel command thread; and
updating the second portion of memory in response to executing the command of the selected command thread if the selected command thread is the vertex command thread.
26. The method of claim 23 , further comprising:
providing an executed command thread to a render backend circuit if the executed command thread is the pixel command thread; and
providing, the executed command thread to a scan converter circuit if the executed command thread is the vertex command thread.