IP Library Granted Patent US 9,582,664
Granted Patent B2
US 9,582,664 · App. 14/299,943 · Granted Feb 28, 2017

Detection of fault injections in a random number generator

Inventor: Yannick Teglia (Belcodene, FR)
Assignee: STMicroelectronics (Rousset) SAS
G06F21/556G06F7/58
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,582,664
App. No.
14/299,943
Granted
Feb 28, 2017
Kind
B2
Abstract

A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.

Claims (44)

1. A method, comprising:

mixing a bit pattern with a bit stream originating from a noise source to generate a mixed bit sequence;

sampling the mixed bit sequence to detect the bit pattern in the mixed bit sequence;

generating a fault injection signal based on whether the sampling detects the bit pattern in the mixed bit sequence; and

selectively performing, based on the fault injection signal, a cyphering operation based at least in part on the mixed bit sequence.

2. The method of claim 1 wherein the mixing comprises interposing one or several bits of the bit pattern between one or several bits of the bit stream.

3. The method of claim 1 , comprising storing said bit pattern in a circuit configured to perform the sampling.

4. The method of claim 1 wherein the bit pattern is a determined bit sequence.

5. The method of claim 1 wherein the bit pattern is a randomly generated bit sequence.

6. The method of claim 1 wherein the bit pattern is a secret key.

7. The method of claim 1 wherein when the fault injection signal indicates the bit pattern is present in the mixed bit sequence, the cyphering operation comprises generating a random number using the mixed bit sequence.

8. The method of claim 7 wherein generating the random number using the mixed bit sequence comprises:

encrypting the mixed bit sequence to generate a word; and

applying a resilient function to the word to generate the random number.

9. The method of claim 1 wherein the cyphering operation comprises at least one encryption operation.

10. A device, comprising:

a bit mixer configured to mix a bit pattern with a bit stream originating from a noise source to generate a mixed bit sequence;

an injection detector configured to sample the mixed bit sequence and determine based on the sampling whether the bit pattern is present in the mixed bit sequence; and

a word generator configured to generate a word from the mixed bit sequence, wherein when the injection detector determines the bit pattern is missing from the mixed bit sequence, the injection detector is configured to generate an indication of an injection attack.

11. The device of claim 10 wherein the bit mixer is configured to interpose one or several bits of the bit pattern between one or several bits of the bit stream.

12. The device of claim 10 wherein the injection detector is configured to store said bit pattern.

13. The device of claim 10 wherein the bit pattern comprises at least one of:

a determined bit sequence;

a randomly generated bit sequence; and

a secret key.

14. The device of claim 10 wherein the word generator is configured to generate the word by encrypting the mixed bit sequence.

15. The device of claim 14 , comprising:

a resilient function block configured to apply a resilient function to the word to generate a random number.

16. The device of claim 10 , comprising:

a second bit mixer configured to mix a second bit pattern into the mixed bit stream.

17. The device of claim 10 , comprising:

a crypto-processor configured to use words generated by the word generator to perform cyphering operations.

18. The device of claim 10 wherein, in operation, the word generator responds to the generation of the indication of an injection attack by not generating the word.

19. A system, comprising:

a processor;

a memory; and

a random number generator configured to generate a random number by:

mixing a bit pattern with a bit stream originating from a noise source to generate a mixed bit sequence;

sampling the mixed bit sequence; and

determining based on the sampling whether the bit pattern is present in the mixed bit sequence, wherein when the random number generator determines the bit pattern is missing from the mixed bit sequence, the random number generator is configured to inhibit generation of the random number.

20. The system of claim 19 wherein the random number generator is configured to interpose one or several bits of the bit pattern between one or several bits of the bit stream.

21. The system of claim 19 wherein the random number generator is configured to generate a word by encrypting the mixed bit sequence and to apply a resilient function to the word to generate the random number.

22. The system of claim 19 , comprising:

a crypto-processor configured to use random numbers generated by the random number generator to perform cyphering operations.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2023
From: STMICROELECTRONICS (ROUSSET) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 063282/0118 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2014
From: TEGLIA, YANNICK
To: STMICROELECTRONICS (ROUSSET) SAS
Reel/Frame 033179/0331 →
Priority Claims (2)
FR 13 55354 · Jun 11, 2013 · national
FR 13 55355 · Jun 11, 2013 · national
Continuity (1)
Related Publication 20140366135A1 · Dec 11, 2014