Plasmonic IR devices

1. An infra-red (IR) device comprising:

a dielectric membrane formed on a silicon substrate, wherein the silicon substrate comprises an etched portion; and

at least one patterned layer formed within or on the dielectric membrane for controlling IR emission or IR absorption of the IR device,

wherein the at least one patterned layer comprises laterally spaced structures.

2. An IR device according to claim 1 , wherein the device is an IR source in which the patterned layer is configured to control the IR emission of the device.

3. An IR device according to claim 2 , further comprising a resistive heater embedded within the dielectric membrane.

4. An IR device according to claim 3 , wherein the resistive heater comprises single crystal silicon or polysilicon.

5. An IR device according to claim 3 , wherein the resistive heater comprises a CMOS-based metal comprising aluminium, copper, titanium, molybdenum or tungsten.

6. An IR device according to claim 3 , wherein the resistive heater comprises platinum.

7. An IR device according to claim 3 , further comprising a titanium/titanium nitride layer adjacent the resistive heater to act as an adhesive, or anti diffusion layer.

8. An IR device according to claim 1 , wherein the dielectric membrane comprises one or more layers of silicon dioxide and/or silicon nitride.

9. An IR device according to claim 1 , wherein each structure comprises a metal comprising gold or platinum, or a CMOS-based metal chosen from among aluminium, copper, titanium, molybdenum and tungsten.

10. An IR device according to claim 9 , further comprising a titanium/titanium nitride layer adjacent the patterned layer to act as an adhesive, or anti diffusion layer.

11. An IR device according to claim 1 , wherein the patterned layer comprises single crystal silicon or polysilicon.

12. An IR device according to claim 3 , wherein the patterned layer comprising the laterally spaced structures is below the heater.

13. An IR device according to claim 3 , wherein the patterned layer comprising the laterally spaced structures is above the heater.

14. An IR device according to claim 1 , wherein the patterned layer comprising the laterally spaced structures is above the membrane.

15. An IR device according to claim 3 , wherein the patterned layer forms part of the layer which forms the resistive heater.

16. An IR device according to claim 1 , wherein the laterally spaced structures are a pattern of dots, and wherein the dots have a shape of a circle, a rectangle, a square, a trapezoid, a hexagon, or a cross.

17. An IR device according to claim 1 , wherein the laterally spaced structures are a pattern of holes, and wherein the holes have a shape of a circle, a rectangle, a square, a trapezoid, a hexagon, or a cross.

18. An IR device according to claim 1 , wherein the laterally spaced structures have a square, rectangular or hexagonal pattern.

19. An IR device according to claim 3 , further comprising a plurality of patterned layers each having laterally spaced structures.

20. An IR device according to claim 19 , wherein all of the plurality of layers are above the resistive heater within the dielectric membrane.

21. An IR device according to claim 19 , wherein all of the plurality of layers having the laterally spaced structures have the same pattern.

22. An IR device according to claim 19 , wherein each of the patterned layers having the laterally spaced structures has a different pattern.

23. An IR device according to claim 1 , further comprising a temperature sensor located within the dielectric membrane.

24. An IR device according to claim 23 , wherein the temperature sensor is a diode, or a resistive temperature sensor comprising a metal or polysilicon or single crystal silicon.

25. An IR device according to claim 3 , further comprising a plurality of resistive heaters located within the membrane.

26. An IR device according to claim 1 , further comprising a spreading plate located within the membrane, the spreading plate comprising single crystal silicon, polysilicon or a metal.

27. An IR device according to claim 3 , wherein the IR source is a CMOS based IR source in which the resistive heater comprises a CMOS interconnect metal, and the dielectric membrane comprises CMOS dielectric layers.

28. An IR device according to claim 27 , wherein the silicon substrate is a bulk silicon substrate.

29. An IR device according to claim 27 , wherein the silicon substrate is an SOI substrate.

30. An IR device according to claim 27 , further comprising circuitry integrated on the same chip as the IR source.

31. An IR device according to claim 3 , wherein the resistive heater is ring, meander, multiring or spiral shaped.

32. An IR device according to claim 3 , wherein the heater is circular.

33. An IR device according to claim 3 , wherein the heater is rectangular.

34. An IR device according to claim 3 , wherein the membrane is circular.

35. An IR device according to claim 1 , wherein the membrane is a square or rectangular.

36. An IR device according to claim 1 , wherein the membrane has a square or rectangular shape with rounded corners.

37. An IR device according to claim 1 , wherein the patterned layers comprise circular dots having a constant diameter which is optionally in the range of about 0.5 μm to 10 μm, and a constant pitch which is optionally in the range of about 1 to 20 μm.

38. An IR device according to claim 1 , wherein the patterned layer is shaped for the lower wavelengths between 2 to 5 μm, such as for carbon dioxide absorption wavelengths.

39. An IR device according to claim 1 , wherein the patterned layer is shaped for the higher wavelengths between 5-15 μm in a Mid-IR region.

40. An IR device according to claim 27 , wherein the heater is formed from a first metal layer formed in the CMOS processing steps.

41. An IR device according to claim 40 , wherein the patterned layer is formed from a top metal layer formed in the CMOS processing steps.

42. An IR device according to claim 41 , wherein the patterned layer comprises circular dots in a hexagonal pattern and the hexagonal pattern is optimised such that the patterned layer is configured to emit at the carbon dioxide absorption wavelength.

43. An array of IR sources incorporating an IR source according to claim 2 , wherein the array of IR sources is arranged on the same chip.

44. An array of IR sources according to claim 43 , wherein each IR source in the array is identical.

45. An array IR source according to claim 44 , wherein the IR sources in the array are different.

46. An IR device according to claim 1 , wherein the IR device is an IR detector in which the patterned layer is configured to control the IR absorption of the device.

47. An IR device according to claim 46 , further comprising a thermopile located within the dielectric membrane, the thermopile comprising a plurality of thermocouples electrically connected in series with one junction inside the membrane and another junction outside the membrane.

48. An IR device according to claim 47 , wherein the thermocouple comprises at least two materials selected from: single crystal silicon, polysilicon, a non-CMOS metal selected from platinum or gold, and a CMOS metal selected from tungsten, copper, aluminium, molybdenum or titanium.

49. An IR device according to claim 47 , wherein each thermocouple has a same length.

50. An IR device according to claim 47 , wherein each thermocouple has a different length.

51. An IR device according to claim 47 , wherein the patterned layer is formed of the same material forming the thermopile of the IR detector.

52. An IR device according to claim 46 , wherein the IR detector is on the same chip as an IR emitter.

53. A method of manufacturing an IR device, the method comprising:

forming a dielectric membrane on a semiconductor substrate, wherein the semiconductor substrate comprises an etched portion; and

forming at least one patterned layer within or on the dielectric membrane for controlling IR emission or IR absorption of the IR device, wherein the at least one patterned layer comprises laterally spaced structures.

54. A method according to claim 53 , wherein the dielectric membrane is formed by anisotropic wet etching resulting is slanting sidewalls of the trench.

55. A method according to claim 53 , wherein the dielectric membrane is formed by Deep Ion Etching (DRIE), resulting in near vertical sidewalls of the trench.