Method of fabricating semiconductor integrated circuit having phase-change layer

1. A method of fabricating a semiconductor integrated circuit, the method comprising:

forming a lower electrode in a semiconductor substrate;

forming an interlayer insulating layer;

etching the interlayer insulating layer to form a hole for exposing the lower electrode;

forming an insulating spacer on a sidewall of the hole;

forming a first phase-change layer having a crystalline state along surfaces of the spacer and an exposed lower electrode;

forming a second phase-change layer on the first phase-change layer based on crystallinity of the first phase-change layer to be filled in the hole under an amorphous deposition conditions;

forming a resistive layer by planarizing the second phase-change layer and the first phase-change layer to be left in the hole; and

forming an upper electrode on the resistive layer,

wherein a bottom surface and a sidewall of the second phase-change layer are contacted with the first phase-change layer with maintaining the crystalline state and an upper surface of the second phase-change layer is contacted with the upper electrode.

2. The method of claim 1 , wherein the first phase-change layer is formed at a crystallization temperature of the first phase-change layer through a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

3. The method of claim 1 , wherein the second phase-change layer is formed to have a partially crystalline state by depositing the second phase-change layer along crystals of the first phase-change layer under the amorphous deposition conditions.

4. The method of claim 3 , wherein the second phase-change layer is formed in a temperature range of 200 to 400° C. through an ALD method.

5. The method of claim 1 , further comprising, after the forming of the second phase-change layer or the foiling of the resistive layer:

heat-treating the second phase-change layer.