IP Library Granted Patent US 9,547,031
Granted Patent B2
US 9,547,031 · App. 14/303,881 · Granted Jan 17, 2017

Flipped cell sensor pattern

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Quick Facts
Patent No.
US 9,547,031
App. No.
14/303,881
Granted
Jan 17, 2017
Kind
B2
Abstract

Embodiments of a capacitive sensor array may comprise a plurality of large sensor electrodes and, for each of the large sensor electrodes, a first plurality of small sensor electrodes each capacitively coupled with the large sensor electrode, and each conductively coupled by one of a first set of routing traces to one of a first set of conductors located in a first edge region, and a second plurality of small sensor electrodes capacitively coupled with the large sensor electrode and conductively coupled by a second set of routing traces to a second set of conductors in a second edge region. The first set of routing traces is located in a first routing channel and the second set of routing traces is located in a second routing channel, where the first and second routing channels are located along different sides of the large sensor electrode.

Claims (47)

1. A capacitive sensor array, comprising:

a plurality of large sensor electrodes; and

for each large sensor electrode of the plurality of large sensor electrodes;

a first plurality of small sensor electrodes each capacitively coupled with the large sensor electrode, and each conductively coupled by one of a first set of routing traces to one of a first set of conductors located in a first edge region; and

a second plurality of small sensor electrodes capacitively coupled with the large sensor electrode and conductively coupled by a second set of routing traces to a second set of conductors in a second edge region, wherein:

each of the first plurality of small sensor electrodes is interleaved with a first side of the large sensor electrode according to a first pattern;

each of the second plurality of small sensor electrodes is interleaved with a second opposite side of the large sensor electrode according to a second pattern that is a mirror opposite of the first pattern;

an active sensing region of the capacitive sensor array is located between the first edge region and the second edge region;

the first set of routing traces is located in a first routing channel and the second set of routing traces is located in a second routing channel; and

the first routing channel and the second routing channel are located along the first and second sides respectively of the large sensor electrode;

wherein the plurality of large sensor electrodes and the corresponding interleaved small sensor electrodes are formed from a single layer of conductive material.

2. The capacitive sensor array of claim 1 , wherein each of the first plurality of small sensor electrodes is closer to the first edge region than to the second edge region, wherein each of the second plurality of small sensor electrodes is closer to the second edge region than to the first edge region, and wherein each of the first set of conductors and the second set of conductors is a conductive pad.

3. The capacitive sensor array of claim 1 , wherein for each large sensor electrode of the plurality of large sensor electrodes, at least a portion of the large sensor electrode is located between two interior points of each small sensor electrode of the first and second pluralities of small sensor electrodes.

4. The capacitive sensor array of claim 1 , wherein for each large sensor electrode of the plurality of large sensor electrodes, each small sensor electrode of the first plurality of small sensor electrodes is conductively coupled with an adjacent small sensor electrode that is capacitively coupled with an adjacent large sensor electrode of the plurality of large sensor electrodes.

5. The capacitive sensor array of claim 1 , wherein for at least one routing trace of the first set of routing traces, at least a portion of the routing trace is located between two other routing traces that are conductively coupled to each other.

6. The capacitive sensor array of claim 1 , wherein for each large sensor electrode of the plurality of large sensor electrodes, each routing trace of the first set and the second set of routing traces is shorter than the large sensor electrode.

7. The capacitive sensor array of claim 1 , wherein for each large sensor electrode of the plurality of large sensor electrodes, a central longitudinal axis of the large sensor electrode intersects each small sensor electrode of the first and second sets of small sensor electrodes.

8. A capacitive sensor array, comprising:

a plurality of column sensor electrodes, wherein each column sensor electrode of the plurality of column sensor electrodes comprises a main trace extending from a first end of the column sensor electrode to a second end of the column sensor electrode; and

for each column sensor electrode of the plurality of column sensor electrodes:

a first plurality of row sensor electrodes, each capacitively coupled with the column sensor electrode and each conductively coupled by one of a first set of routing traces to a first edge region; and

a second plurality of row sensor electrodes, each capacitively coupled with the column sensor electrode and each conductively coupled by one of a second set of routing traces to a second edge region on an opposite side of an active sensing area of the capacitive sensor array from the first edge region, wherein:

each of the first plurality of row sensor electrodes is interleaved with a first side of the column sensor electrode according to a first pattern;

each of the second plurality of row sensor electrodes is interleaved with a second opposite side of the column sensor electrode according to a second pattern that is a mirror opposite of the first pattern; and

the first set of routing traces and the second set of routing traces are located along the first and second sides respectively of the column sensor electrode,

the plurality of column sensor electrodes and the corresponding interleaved row sensor electrodes are formed from a same layer of conductive material.

9. The capacitive sensor array of claim 8 , wherein each of the first plurality of row sensor electrodes is closer to the first edge region than to the second edge region, and wherein each of the second plurality of row sensor electrodes is closer to the second edge region than to the first edge region.

10. The capacitive sensor array of claim 8 , wherein for each column sensor electrode of the plurality of column sensor electrodes, each row sensor electrode of the first plurality of row sensor electrodes is conductively coupled with an adjacent row sensor electrode that is capacitively coupled with an adjacent column sensor electrode of the plurality of column sensor electrodes.

11. The capacitive sensor array of claim 8 , wherein for at least one routing trace of the first set of routing traces, at least a portion of the routing trace is located between two other routing traces that are conductively coupled to each other.

12. The capacitive sensor array of claim 8 , wherein for each column sensor electrode of the plurality of column sensor electrodes, each routing trace of the first set and the second set of routing traces is shorter than the column sensor electrode.

13. The capacitive sensor array of claim 8 , wherein for each column sensor electrode of the plurality of column sensor electrodes, a central longitudinal axis of the column sensor electrode intersects each row sensor electrode of the first and second sets of row sensor electrodes.

14. A capacitance sensing system, comprising:

a capacitance sensor;

a plurality of large sensor electrodes of a capacitive sensor array, each of the large sensor electrodes coupled with the capacitance sensor; and

for each large sensor electrode of the plurality of large sensor electrodes:

a first plurality of small sensor electrodes coupled with the capacitance sensor, each capacitively coupled with the large sensor electrode, and each conductively coupled by a first set of routing traces to at least one of a first set of conductors in a first edge region; and

a second plurality of small sensor electrodes coupled with the capacitance sensor, each capacitively coupled with the large sensor electrode, and each conductively coupled by a second set of routing traces to at least one of a second set of conductors in a second edge region, wherein:

each of the first plurality of small sensor electrodes is interleaved with a first side of the large sensor electrode according to a first pattern;

each of the second plurality of small sensor electrodes is interleaved with a second opposite side of the large sensor electrode according to a second pattern that is a mirror opposite of the first pattern;

an active sensing region of the capacitive sensor array is located between the first edge region and the second edge region;

the first set of routing traces is located in a first routing channel and the second set of routing traces is located in a second routing channel;

the first routing channel and the second routing channel are located along the first and second sides respectively of the large sensor electrode;

wherein the plurality of large sensor electrodes and the corresponding interleaved small sensor electrodes are formed from a single layer of conductive material.

15. The capacitance sensing system of claim 14 , wherein the capacitance sensor is configured to measure mutual capacitances between each of the plurality of large sensor electrodes and each of the plurality of small sensor electrodes.

16. The capacitance sensing system of claim 14 , wherein for the first set of routing traces, a portion of at least one of the first set of routing traces is located between two other routing traces of the first set of routing traces that are conductively coupled to each other.

17. The capacitance sensing system of claim 14 , wherein each large sensor electrode has a rotational symmetry with respect to a center point of the respective large sensor electrode.

18. The capacitance sensing system of claim 14 , wherein the plurality of large sensor electrodes includes a first large sensor electrode and a second sensor electrode that are disposed adjacent to each other, and the first large sensor electrode and its corresponding first and second pluralities of small sensor electrodes mirror the second large sensor electrode and its corresponding first and second pluralities of small sensor electrodes.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION
To: PARADE TECHNOLOGIES, LTD.
Reel/Frame 036508/0284 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS Recorded Aug 4, 2015
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT FOR THE SECURED PARTIES
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036264/0114 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2014
From: WENG, XIAOPING; DENG, YINGZHU; AVERY, BENJAMIN
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 033479/0800 →