Method and system for a feedback transimpedance amplifier with sub-40khz low-frequency cutoff
View Patent ↗A system for a feedback amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing an amplifier having feedback paths comprising source followers and feedback resistors. Gate terminals of the source followers may be coupled to output terminals of the amplifier circuit. The feedback paths may be coupled prior to the coupling capacitors at inputs of the amplifier circuit. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the amplifier circuit. The amplifier circuit may be integrated in a CMOS photonics chip with the source followers comprising CMOS transistors. The amplifier circuit may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode differentially coupled to the amplifier circuit. Optical signals for the photodetector in the chip may be received via optical fibers.
1. A system for processing electrical signals, the system comprising:
an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source followers and feedback resistors, said feedback paths being coupled prior to said coupling capacitors at inputs of said gain stage, said gain stage amplifying electrical signals received via said coupling capacitors, and gate terminals of said source followers being coupled to output terminals of said gain stage.
2. The system according to claim 1 , wherein said source followers are operable to level shift voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.
3. The system according to claim 1 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.
4. The system according to claim 3 , wherein said CMOS chip comprises a CMOS photonics chip.
5. The system according to claim 4 , wherein said CMOS photonics chip receives optical signals for said photodetector via one or more optical fibers.
6. The system according to claim 1 , wherein said source followers comprise CMOS transistors.
7. The system according to claim 1 , wherein said gain stage receives current-mode logic signals.
8. The system according to claim 1 , wherein said gain stage receives voltage signals.
9. The system according to claim 1 , wherein said electrical signals are received from a photodetector.
10. The system according to claim 9 , wherein said photodetector comprises a silicon germanium photodiode.
11. The system according to claim 9 , wherein said photodetector is differentially coupled to said gain stage.
12. A method for processing optical signals, the method comprising:
in an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source followers and feedback resistors, said feedback paths being coupled prior to said coupling capacitors at inputs of said gain stage, and gate terminals of said source followers being coupled to output terminals of said gain stage,
amplifying electrical signals received via said coupling capacitors utilizing said gain stage.
13. The method according to claim 12 , comprising level shifting voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.
14. The method according to claim 12 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.
15. The method according to claim 14 , wherein said CMOS chip comprises a CMOS photonics chip.
16. The method according to claim 12 , comprising receiving said electrical signals from a photodetector.
17. The method according to claim 16 , comprising receiving optical signals for said photodetector in said CMOS photonics chip via one or more optical fibers.
18. The method according to claim 16 , wherein said photodetector comprises a silicon germanium photodiode.
19. The method according to claim 16 , wherein said photodetector is differentially coupled to said gain stage.
20. The method according to claim 12 , wherein said source followers comprise CMOS transistors.
21. The method according to claim 12 , wherein said gain stage receives current-mode logic signals.
22. The method according to claim 12 , wherein said gain stage received voltage signals.