IP Library Granted Patent US 9,087,873
Granted Patent B2
US 9,087,873 · App. 14/306,923 · Granted Jul 21, 2015

Semiconductor device manufacturing method

Inventor: Tamotsu Owada (Yokohama, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H01L21/76251H01L29/0657
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Quick Facts
Patent No.
US 9,087,873
App. No.
14/306,923
Granted
Jul 21, 2015
Kind
B2
Abstract

A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. The first face of the device wafer and the bonding face of the support substrate are bonded together by an adhesive. The device wafer is ground from a second face side, on the opposite side to the first face 11 , as far as a depth position to reach a bottom face of the recessed portion.

Claims (18)

1. A semiconductor device manufacturing method, comprising:

forming a first recessed portion around an outer edge of a device wafer, at a peripheral edge portion of a first face of the device wafer;

forming a second recessed portion around an outer edge of a support substrate, at a bonding face of the support substrate;

bonding together the first face of the device wafer and the bonding face of the support substrate via an adhesive; and

grinding the device wafer from a second face side that is at an opposite side to the first face as far as a depth position that reaches a bottom face of the first recessed portion.

2. The manufacturing method of claim 1 , further comprising forming a first adhesion layer, that increases adhesion with respect to the adhesive, at a surface of the second recessed portion.

3. The manufacturing method of claim 2 , further comprising forming a second adhesion layer, that increases adhesion with respect to the adhesive, at a surface of the first recessed portion.

4. The manufacturing method of claim 3 , wherein the first adhesion layer and the second adhesion layer include a silane coupling agent.

5. The manufacturing method of claim 1 , further comprising forming a low adhesion layer that has reduced adhesion with respect to the adhesive and that is disposed further inward of the bonding face of the support substrate than the second recessed portion.

6. The manufacturing method of claim 1 , wherein:

the first recessed portion is formed by partially removing a region that includes an end face of the outer edge of the device wafer; and

the second recessed portion is formed by partially removing a region that includes an end face of the outer edge of the support substrate.

7. The manufacturing method of claim 1 , wherein the second recessed portion includes a plurality of grooves provided around the outer edge of the support substrate.

8. The manufacturing method of claim 1 , wherein:

the first recessed portion is formed by partially removing a region that is further inward than an end face that forms the outer edge of the device wafer; and

the second recessed portion is formed by partially removing a region that is further inward than an end face that forms the outer edge of the support substrate.

9. The manufacturing method of claim 1 , further comprising separating the support substrate from the device wafer after the device wafer has been ground.

10. The manufacturing method of claim 1 , wherein the first recessed portion is formed by removing a beveled portion of the device wafer at the first face side.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2014
From: OWADA, TAMOTSU
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033122/0028 →
Priority Claims (1)
JP 2013-145737 · Jul 11, 2013 · national
Continuity (1)
Related Publication 20150014820A1 · Jan 15, 2015