IP Library Granted Patent US 9,391,551
Granted Patent B2
US 9,391,551 · App. 14/307,643 · Granted Jul 12, 2016

Apparatus to detect the zero-cross of the BEMF of a three-phase electric motor and related method

Inventors: Michele Boscolo Berto (Milan, IT); Federico Magni (Settimo Milanese, IT)
Assignee: STMICROELECTRONICS S.R.L.
H02P6/182
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Quick Facts
Patent No.
US 9,391,551
App. No.
14/307,643
Granted
Jul 12, 2016
Kind
B2
Abstract

A device may detect the zero-cross event of a BEMF of an electric motor with first, second, and third phase windings driven by respective first, second, and third power driving stages. The device may include a control circuit configured to place at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being coupled to a zero-cross detecting circuit, introduce a masking signal to mask an output signal of the zero-cross detecting circuit in correspondence with each rising edge of a first driving signal of the first power driving stage relative to the first phase winding, and determine whether a first duty-cycle of the first driving signal is such that a duration of a masking window of the masking signal is greater than an on-time period of the first driving signal.

Claims (57)

1. Apparatus to detect a zero-cross event of a back electromotive force (BEMF) of an electric motor with first, second, and third phase windings driven by respective first, second, and third power driving stages, the apparatus comprising:

a zero-cross detecting circuit; and

a control circuit configured to control the first, second, and third power driving stages by at least

placing at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being coupled to said zero-cross detecting circuit,

driving the first power driving stage relative to the first phase winding with a first pulse width modulated (PWM) driving signal,

introducing a masking signal to mask an output signal of said zero-cross detecting circuit in correspondence with each rising edge of the first PWM driving signal, and

determining whether a first duty-cycle of the first PWM driving signal relative to the first phase winding is such that a duration of a masking window of the masking signal is greater than an on-time period of the first PWM driving signal, and if then,

driving the second power driving stage relative to the second phase winding with a second PWM driving signal with a second duty-cycle greater than zero, and

modifying the first duty-cycle to have a duration of the on-time period of the first PWM driving signal greater than the masking window of the masking signal.

2. The apparatus according to claim 1 wherein said control circuit, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, is configured to:

set a value of the second duty-cycle to be one minus the first duty-cycle; and

set an on-time period and an off-time period of the second PWM driving signal to correspond respectively to an off-time period and the on-time period of the first PWM driving signal.

3. The apparatus according to claim 1 wherein said control circuit, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, is configured to:

set a value of the second duty-cycle to be one minus the first duty-cycle; and

place at the impedance state the first and second power driving stages only during an off-time period of the first PWM driving signal.

4. The apparatus according to claim 1 wherein the control circuit, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, is configured to:

set a new value of the first duty-cycle of the first PWM driving signal to be half of the first duty-cycle plus 0.5; and

set the second duty-cycle of the second PWM driving signal to be one minus the first duty-cycle.

5. The apparatus according to claim 1 wherein the electric motor comprises a permanent magnet synchronous motor (PMSM).

6. The apparatus according to claim 1 wherein the masking signal has a duration equal to 50% of a switching period of at least one of the first and the second PWM driving signals.

7. A control circuit for detecting a zero-cross event of a back electromotive force (BEMF) of an electric motor with first, second, and third phase windings driven by respective first, second, and third power driving stages, the control circuit comprising:

circuitry configured to

place at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being coupled to a zero-cross detecting circuit,

drive the first power driving stage relative to the first phase winding with a first pulse width modulated (PWM) driving signal,

introduce a masking signal to mask an output signal of the zero-cross detecting circuit in correspondence with each rising edge of the first PWM driving signal, and

determine whether a first duty-cycle of the first driving signal relative to the first phase winding is such that a duration of a masking window of the masking signal is greater than an on-time period of the first driving signal, and if then,

drive the second power driving stage relative to the second phase winding with a second driving signal with a second duty-cycle greater than zero, and

modify the first duty-cycle to have a duration of the on-time period of the first driving signal, the first duty-cycle being greater than the masking window of the masking signal.

8. The control circuit according to claim 7 wherein said circuitry, if the first duty-cycle of the first driving signal is such that the duration of the masking window is greater than the on-time period of the first driving signal, is configured to:

set a value of the second duty-cycle to be one minus the first duty-cycle; and

set an on-time period and an off-time period of the second driving signal to correspond respectively to an off-time period and the on-time period of the first driving signal.

9. The control circuit according to claim 7 wherein said circuitry, if the first duty-cycle of the first driving signal is such that the duration of the masking window is greater than the on-time period of the first driving signal, is configured to:

set a value of the second duty-cycle to be one minus the first duty-cycle; and

place at the impedance state the first and second power driving stages only during an off-time period of the first driving signal.

10. The control circuit according to claim 7 wherein the circuitry, if the first duty-cycle of the first driving signal is such that the duration of the masking window is greater than the on-time period of the first driving signal, is configured to:

set a new value of the first duty-cycle of the first driving signal to be half of the first duty-cycle plus 0.5; and

set the second duty-cycle of the second driving signal to be one minus the first duty-cycle.

11. The control circuit according to claim 7 wherein the electric motor comprises a permanent magnet synchronous motor (PMSM).

12. The control circuit according to claim 7 wherein the masking signal has a duration equal to 50% of a switching period of at least one of the first and the second driving signals.

13. A method for detecting a zero-cross event of a back electromotive force (BEMF) of an electric motor with first, second, and third phase windings driven by respective first, second, and third power driving stages, the method comprising:

placing at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being coupled to a zero-cross detecting circuit;

driving the first power driving stage relative to the first phase winding with a first pulse width modulated (PWM) driving signal;

introducing a masking signal to mask an output signal of the zero-cross detecting circuit in correspondence with each rising edge of the first PWM driving signal; and

determining whether a first duty-cycle of the first PWM driving signal relative to the first phase winding is such that a duration of a masking window of the masking signal is greater than an on-time period of the first PWM driving signal, and if then;

driving the second power driving stage relative to the second phase winding with a second PWM driving signal with a second duty-cycle greater than zero, and

modifying the first duty-cycle to have a duration of the on-time period of the first PWM driving signal greater than the masking window of the masking signal.

14. The method according to claim 13 wherein, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, further comprising:

setting a value of the second duty-cycle to be one minus the first duty-cycle; and

setting an on-time period and an off-time period of the second PWM driving signal to correspond respectively to an off-time period and the on-time period of the first PWM driving signal.

15. The method according to claim 13 wherein, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, further comprising:

setting a value of the second duty-cycle to be one minus the first duty-cycle; and

placing at the impedance state the first and second power driving stages only during an off-time period of the first PWM driving signal.

16. The method according to claim 13 wherein, if the first duty-cycle of the first PWM driving signal is such that the duration of the masking window is greater than the on-time period of the first PWM driving signal, further comprising:

setting a new value of the first duty-cycle of the first PWM driving signal to be half of the first duty-cycle plus 0.5; and

setting the second duty-cycle of the second PWM driving signal to be one minus the first duty-cycle.

17. The method according to claim 13 wherein the electric motor comprises a permanent magnet synchronous motor (PMSM).

18. The method according to claim 13 wherein the masking signal has a duration equal to 50% of a switching period of at least one of the first and the second PWM driving signals.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060301/0355 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST INVENTOR'S NAME PREVIOUSLY RECORDED AT REEL: 033140 FRAME: 0850. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2016
From: BOSCOLO BERTO, MICHELE; MAGNI, FEDERICO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 038182/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2014
From: BOSCOLO, MICHELE BERTO; MAGNI, FEDERICO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 033140/0850 →
Priority Claims (1)
IT MI2013A1082 · Jun 28, 2013 · national
Continuity (1)
Related Publication 20150002065A1 · Jan 1, 2015