IP Library Granted Patent US 9,425,690
Granted Patent B2
US 9,425,690 · App. 14/309,314 · Granted Aug 23, 2016

Current controlling mode direct current (DC)-DC converter

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Quick Facts
Patent No.
US 9,425,690
App. No.
14/309,314
Granted
Aug 23, 2016
Kind
B2
Abstract

There is provided a current controlling mode DC-DC converter that operates in a PWM mode or a PFM mode by adjusting a turned-on time of a gate depending on power consumption of a load. The DC-DC converter includes a first comparator that receives a first input voltage and a second input voltage and outputs a first output signal, a second comparator that receives a reference voltage for mode switching and the second input voltage and outputs a second output signal, and a first logic element that outputs a reset signal for turning off a gate at a point of time when both the first output signal and the second output signal are applied. Examples may also include additional elements to facilitate mode switching.

Claims (32)

1. A direct current (DC)-DC converter, comprising:

a first comparator configured to receive a first input voltage and a second input voltage and to output a first output signal;

a second comparator configured to receive a reference voltage configured to indicate mode switching and the second input voltage and to output a second output signal, wherein the second input voltage is based on a sensing signal and a ramp signal; and

a first logic element configured to output a reset signal based upon a determination that both the first output signal and the second output signal are applied to the first logic element, wherein the reset signal is configured to turn off a gate.

2. The DC-DC converter of claim 1 , wherein the first input voltage comprises an output voltage of an error amplifier.

3. The DC-DC converter of claim 2 , wherein the inputs of the error amplifier comprise a reference voltage for controlling a feedback voltage.

4. The DC-DC converter of claim 1 , further comprising:

an inverter configured to invert the first output signal;

a second logic element configured to receive a clock signal and an output signal of the inverter and to output a set signal; and

an Set-Reset (SR) latch configured to receive the reset signal or the set signal and configured to generate a waveform in which an on-time section of the gate has been adjusted.

5. The DC-DC converter of claim 4 , wherein the first logic configured to output the reset signal and the second logic element configured to output the set signal are AND gates.

6. The DC-DC converter of claim 4 , wherein the reference comprises a minimum on-time value of the gate that enables the DC-DC converter to operate in a Pulse Width Modulation (PWM) mode.

7. The DC-DC converter of claim 4 , wherein the DC-DC converter operates in a Pulse Width Modulation (PWM) mode in a section of gate operation in which the first input voltage is larger than the reference voltage.

8. The DC-DC converter of claim 7 , wherein in the PWM mode, the first output signal is generated later than the second output signal.

9. The DC-DC converter of claim 7 , wherein the on-time section of the gate becomes narrower based on a decrease in the first input voltage in the PWM mode.

10. The DC-DC converter of claim 7 , wherein a width of the second output signal becomes narrower based on a decrease in the first input voltage in the PWM mode.

11. The DC-DC converter of claim 4 , wherein the DC-DC converter operates in a Pulse Frequency Modulation (PFM) mode in a section of gate operation in which the first input voltage is smaller than the reference voltage.

12. The DC-DC converter of claim 11 , wherein in the PFM mode, the first output signal is generated earlier than the second output signal.

13. The DC-DC converter of claim 11 , herein in the PFM mode, the on-time section of the gate is constant.

14. The DC-DC converter of claim 11 , wherein the gate is maintained in a turned-off state in a section in which the first input voltage is smaller than an initial voltage of the second input voltage.

15. The DC-DC converter of claim 4 , wherein the DC-DC converter changes from Pulse Width Modulation (PWM) mode to Pulse Frequency Modulation (PFM) mode or from PFM mode to PWM mode in a section of gate operation in which the first input voltage is equal to the reference voltage.

16. A direct current (DC)-DC converter, comprising:

a first comparator configured to receive a first input voltage and a second input voltage and to output a first output signal;

a second comparator configured to receive a reference voltage for mode switching and the second input voltage and to output a second output signal;

a first logic element configured to output a reset signal based upon a determination that both the first output signal and the second output signal are applied to the first logic element, wherein the reset signal is configured to turn off a gate; and

a second logic element configured to output a set signal based upon a determination that a clock signal and an inverted first output signal are applied to the second logic element, wherein the set signal is configured to turn on the gate,

wherein the DC-DC converter switches between modes by outputting a reset signal for a gate at a point in time at which both the first output signal and the second output signals are applied, and

wherein the DC-DC converter changes from Pulse Width Modulation (PWM) mode to Pulse Frequency Modulation (PFM) mode or from PFM mode to PWM mode in a section of gate operation in which the first input voltage is equal to the reference voltage.

17. The DC-DC converter of claim 16 , wherein the first input voltage comprises an output voltage of an error amplifier.

18. The DC-DC converter of claim 17 , wherein the inputs of the error amplifier comprise a reference voltage for controlling a feedback voltage.

19. The DC-DC converter of claim 16 , wherein the second input voltage comprises a combined signal of a sensing signal and a ramp signal.

20. The DC-DC converter of claim 16 , wherein the DC-DC converter operates in a Pulse Width Modulation (PWM) mode in a section of gate operation in which the first input voltage is larger than the reference voltage and operates in a Pulse Frequency Modulation (PFM) mode in a section of gate operation in which the first input voltage is smaller than the reference voltage.

Assignments (3)
NUNC PRO TUNC ASSIGNMENT Recorded Feb 18, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 070241/0214 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2014
From: MIN, JUN SIK; KIM, HYOUNG KYU
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 033141/0375 →