IP Library Granted Patent US 9,461,104
Granted Patent B2
US 9,461,104 · App. 14/309,357 · Granted Oct 4, 2016

Semiconductor device integrating a voltage divider and process for manufacturing a semiconductor device

Inventors: Vincenzo Palumbo (Vimercate, IT); Mirko Venturato (Cabiate, IT)
Assignee: STMICROELECTRONICS S.R.L.
H01L28/20H01L23/5225H01L23/5228H01L27/0207H01L27/0629H01L29/405H01L29/66681H01L29/7817G01R15/04H01L23/585H01L29/0696H01L29/1095H01L2924/0002
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Quick Facts
Patent No.
US 9,461,104
App. No.
14/309,357
Granted
Oct 4, 2016
Kind
B2
Abstract

A semiconductor device includes: a semiconductor substrate; a high-voltage first resistive structure which extends along a spiral path above the substrate and is separated from the substrate by a first dielectric layer; and a conductive shielding structure, including a plurality of first shielding strips, which are arranged in sequence along respective portions of the first resistive structure and are separated from the first resistive structure by a second dielectric layer.

Claims (30)

1. A semiconductor device comprising:

a semiconductor substrate;

a high-voltage first resistive structure extending along a spiral path above the substrate and separated from the substrate by a first dielectric layer;

a second resistive structure extending along a spiral path above the substrate, separated from the substrate by the first dielectric layer and concentric to the first resistive structure; and

a conductive shielding structure that includes a plurality of first shielding strips arranged in sequence along respective portions of the first resistive structure and separated from the first resistive structure by a second dielectric layer, and a plurality of second shielding strips arranged in sequence along respective portions of the second resistive structure and separated from the second resistive structure by the second dielectric layer, the first shielding strips being separated from one another by a plurality of regions of discontinuity.

2. The semiconductor device according to claim 1 , wherein the first resistive structure has a first terminal, a second terminal and an outlet node and comprises a first resistor between the first terminal and the outlet node, and a second resistor, between the second terminal and the outlet node, the first resistor and the second resistor forming a voltage divider.

3. The semiconductor device according to claim 2 , comprising a supply line, the first resistive structure being coupled between terminals of the supply line.

4. The semiconductor device according to claim 3 , comprising a power component in the substrate in a region corresponding to the first resistive structure, the power component having conduction terminals coupled to the first resistive structure.

5. The semiconductor device according to claim 1 , wherein the first shielding strips are electrically coupled to respective portions of the first resistive structure by plugs arranged through the second dielectric layer.

6. The semiconductor device according to claim 5 , comprising ohmic contact regions in positions corresponding to respective plugs.

7. The semiconductor device according to claim 1 , wherein the first shielding strips are not directly in contact with one another.

8. The semiconductor device according to claim 7 , wherein the first shielding strips have a width substantially equal to a width of the semiconductor strip forming the first resistive structure.

9. The semiconductor device according to claim 1 , wherein the first shielding strips are coplanar with one another and parallel to the first resistive structure.

10. The semiconductor device according to claim 1 , wherein the first resistive structure comprises a semiconductor strip extending along the spiral path.

11. The semiconductor device according to claim 1 , wherein each first shielding strip extends over an angle not greater than 10°, for example, less than 6°.

12. The semiconductor device according to claim 1 , wherein the second shielding strips are electrically coupled to respective portions of the second resistive structure by further plugs arranged through the second dielectric layer.

13. The semiconductor device according to claim 1 wherein the second shielding strips are not directly in contact with one another and with the first shielding strips.

14. A process for manufacturing a semiconductor device comprising:

forming a first dielectric layer on a semiconductor substrate;

forming, on the first dielectric layer, a first resistive structure extending along a first spiral path;

forming, on the first dielectric layer, a second resistive structure extending along a second spiral path, the second resistive structure being concentric to the first resistive structure;

forming a second dielectric layer on the first dielectric layer, so as to incorporate the first resistive structure and the second resistive structure; and

forming a conductive shielding structure, comprising a plurality of first shielding strips arranged in sequence along respective portions of the first resistive structure, and a plurality of second shielding strips arranged in sequence along respective portions of the second resistive structure and separated from the second resistive structure by the second dielectric layer, the first shielding strips being separated from one another by a plurality of regions of discontinuity.

15. The process according to claim 14 , comprising performing an annealing after having formed the shielding structure.

16. The process according to claim 15 , wherein performing an annealing comprises using forming gas.

17. The process according to claim 14 , wherein forming the shielding structure comprises:

forming, in the second dielectric layer, apertures exposing respective portions of the first resistive structure and the second resistive structure;

filling the apertures with a conductive material;

depositing a metallic layer in contact with the conductive material in the apertures; and

shaping the metallic layer so as to obtain the first shielding strips and the second shielding strips.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061828/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2014
From: PALUMBO, VINCENZO; VENTURATO, MIRKO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 033145/0001 →
Priority Claims (1)
IT TO2013A0541 · Jun 28, 2013 · national
Continuity (1)
Related Publication 20150001677A1 · Jan 1, 2015