LDMOS device and structure for bulk FinFET technology
View Patent ↗A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
1. A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation, the device comprising:
a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions comprising substrate material, wherein the one or more non-well regions are configured to separate well regions of the two or more second-well regions;
a source structure disposed on a first fin partially formed on the first-well region;
a drain structure disposed on a second fin formed on a last one of the two or more second-well regions; and
one or more dummy regions formed on the one or more non-well regions, wherein the one or more dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
2. The device of claim 1 , wherein the LDMOS bulk finFET device comprises an NLDMOS bulk finFET device.
3. The device of claim 1 , wherein the LDMOS bulk finFET device comprises a PLDMOS bulk finFET device, the substrate material comprises a deep n-well in silicon, the first-well region comprises an n-well region, the two or more second-well regions comprise p-well regions, and the charge carriers comprise holes.
4. The device of claim 3 , wherein each of the one or more dummy regions comprises a dummy fin formed on one of the one or more non-well regions, wherein each of the one or more dummy regions are configurable to allow the vertical flow paths for charge carriers to pass through the dummy fin.
5. The device of claim 4 , wherein each of the one or more dummy regions comprises a dummy gate disposed on the dummy fin to conform to finFET-based CMOS fabrication process flow, wherein the high-voltage operation of the device is achievable without the dummy gate.
6. The device of claim 1 , wherein the dummy gate is configured to allow the high voltage operation of the device, when coupled to a suitable bias voltage.
7. The device of claim 1 , wherein the device is fabricated using finFET-based CMOS fabrication process flow without additional masks or process steps.
8. The device of claim 1 , wherein the substrate material comprises p-type silicon.
9. The device of claim 1 , wherein the first-well region comprises a p-well region.
10. The device of claim 1 , wherein the two or more second-well regions comprise n-well regions, and the charge carriers comprise electrons.
11. The device of claim 1 , wherein the additional depletion region flow paths are formed at a junction of one of the one or more non-well regions and a dummy fin.
12. The device of claim 11 , wherein the dummy fin is formed on one of the one or more dummy regions.
13. The device of claim 12 , wherein each of the one or more dummy regions are configurable to allow the vertical flow paths for charge carriers to pass through the dummy fin.
14. A method for forming a lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation, the method comprising:
forming a first-well region and two or more second-well regions on a substrate material, wherein the two or more second-well regions are separated by one or more non-well regions;
forming a first fin partially on the first-well region and a second fin on a last one of the two or more second-well regions;
disposing a source structure on the first fin and a drain structure on the second fin; and
forming one or more dummy regions on the one or more non-well regions, wherein the one or more dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
15. The method of claim 14 , wherein forming the LDMOS bulk finFET device comprises forming an NLDMOS bulk finFET device.
16. The method of claim 14 , wherein forming the LDMOS bulk finFET device comprises forming a PLDMOS bulk finFET device, the substrate material comprises a deep n-well in silicon, forming the first-well region comprises forming an n-well region, forming the two or more second-well regions comprises forming p-well regions, and the charge carriers comprise holes.
17. The method of claim 16 , wherein each of the one or more dummy regions comprises a dummy fin formed on one of the one or more non-well regions, and wherein each of the one or more dummy regions are configurable to allow the vertical flow paths for charge carriers to pass through the dummy fin.
18. The method of claim 17 , wherein forming each of the one or more dummy regions comprises disposing a dummy gate on the dummy fin to conform to finFET-based CMOS fabrication process flow, wherein the high-voltage operation of the device is achievable without the dummy gate.
19. The method of claim 14 , further comprising configuring the dummy gate to allow the high voltage operation of the device, when coupled to a suitable bias voltage.
20. The method of claim 14 , further comprising fabricating the MVOS bulk finFET using finFET-based CMOS fabrication process flow without additional masks or process steps.
21. The method of claim 14 , wherein the substrate material comprises p-type silicon.
22. The method of claim 14 , wherein the first-well region comprises a p-well region.
23. The method of claim 14 , wherein forming the two or more second-well regions comprises forming n-well regions, and the charge carriers comprise electrons.
24. The method of claim 14 , further comprising providing the additional depletion region flow paths comprises forming the additional depletion region flow paths at a junction of one the one or more non-well regions and a dummy fin.
25. The method of claim 24 , further comprising forming the dummy fin on one of the one or more dummy regions.
26. The method of claim 25 , further comprising making each of the one or more dummy regions configurable to allow the vertical flow paths for charge carriers to pass through the dummy tin.
27. A communication device, comprising:
A transmitter circuit including a radio-frequency (RF) power amplifier, wherein the RF power amplifier is fabricated using lateral double-diffused MOS (LDMOS) bulk finFET devices for high-voltage operation, each LDMOS bulk finFET device comprising:
a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions comprising substrate material, wherein the one or more non-well regions are configured to separate well regions of the two or more second-well regions;
a source structure disposed on a first fin partially formed on the first-well region;
a drain structure disposed on a second fin formed on a last one of the two or more second-well regions; and
one or more dummy regions formed on the one or more non-well regions, wherein the dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
28. The communication device of claim 27 , wherein each of the one or more dummy regions comprises a dummy fin formed on one of the one or more non-well regions.
29. The communication device of claim 27 , wherein each of the one or more dummy regions are configurable to allow the vertical flow paths for charge carriers to pass through the dummy fin.
30. The communication device of claim 27 , wherein each of the one or more dummy regions comprises a dummy gate disposed on the dummy fin to conform to finFET-based CMOS fabrication process flow, wherein the high-voltage operation of the device is achievable without the dummy gate.
31. The communication device of claim 30 , wherein the dummy gate is configured to allow the high voltage operation of the device, when coupled to a suitable bias voltage.
32. The communication device of claim 27 , wherein the LDMOS bulk finFET device is fabricated using finFET-based CMOS fabrication process flow without additional masks or process steps.
33. A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation, the device comprising:
a substrate formed by a substrate material;
a first-well region formed on the substrate;
two or more second-well regions formed on the substrate;
one or more non-well regions comprising substrate material and configured to separate well regions of the two or more second-well regions;
a first fin partially formed on the first-well region;
a source structure disposed on the first fin;
a second fin formed on a last one of the two or more second-well regions;
a drain structure disposed on the second fin; and
one or more dummy regions formed on the one or more non-well regions and configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
34. The device of claim 33 , wherein the LDMOS bulk finFET device comprises an NLDMOS bulk finFET device, and wherein the device is fabricated using finFET-based CMOS fabrication process flow without additional masks or process steps.