Noise detection circuit and semiconductor system using the same
A noise detection circuit may include a divider configured to receive a clock signal and a clock bar signal, divide the clock signal and the clock bar signal, and generate a first divided signal and a second divided signal. The noise detection circuit may also include a noise detection reference block configured to reflect a power supply voltage level variation on the first divided signal and the second divided signal, and generate a first reference signal and a second reference signal, and a duty sensing circuit configured to generate first duty information and second duty information of the clock signal in response to the first reference signal and the second reference signal. The noise detection circuit may also include a detection circuit configured to generate a noise detection signal in response to the first duty information and the second duty information.
1. A noise detection circuit comprising:
a divider configured to receive a clock signal and a clock bar signal, divide the clock signal and the clock bar signal, and generate a first divided signal and a second divided signal;
a noise detection reference block configured to reflect a power supply voltage level variation on the first divided signal and the second divided signal, and generate a first reference signal and a second reference signal;
a duty sensing circuit configured to generate first duty information and second duty information of the clock signal in response to the first reference signal and the second reference signal; and
a detection circuit configured to generate a noise detection signal in response to the first duty information and the second duty information.
2. The noise detection circuit according to claim 1 , wherein the divider comprises:
a first division logic configured to divide the clock signal and generate the first divided signal;
a first transmission gate configured to transmit the clock signal to the first division logic in response to a control signal;
a second division logic configured to divide the clock bar signal and generate the second divided signal; and
a second transmission gate configured to transmit the clock bar signal to the second division logic in response to the control signal.
3. The noise detection circuit according to claim 1 , wherein the noise detection reference block is configured to delay the first divided signal and the second divided signal by a predetermined time and generate the first reference signal and the second reference signal, and reflect the power supply voltage level variation on the operation of delaying the first divided signal and the second divided signal.
4. The noise detection circuit according to claim 1 , wherein the first duty information may be high pulse width information of the clock signal, and the second duty information may be low pulse width information of the clock signal.
5. The noise detection circuit according to claim 1 , wherein the detection circuit comprises:
a subtractor configured to subtract the first duty information and the second duty information, and generate a first code; and
a first code comparison part configured to compare a stored first reference code with the first code, and generate a duty error determination signal.
6. The noise detection circuit according to claim 5 , further comprising:
an adder configured to add the first duty information and the second duty information, and generate a second code;
a second code comparison part configured to compare a stored second reference code with the second code, and generate a frequency determination signal; and
an output control part configured to generate the noise detection signal in response to the frequency determination signal and the duty error determination signal.
7. The noise detection circuit according to claim 6 , wherein the output control part is configured to activate the noise detection signal when the frequency determination signal and the duty error determination signal are activated.
8. The noise detection circuit according to claim 7 ,
wherein the frequency determination signal is activated when a code value of the second code is equal to or larger than a code value of the stored second reference code, and
wherein the duty error determination signal is activated when a code value of the first code is equal to or larger than a code value of the stored first reference code.
9. The noise detection circuit according to claim 1 , wherein the detection circuit further comprises:
a subtractor configured to subtract the first duty information and the second duty information, and generate a first code;
an adder configured to add the first duty information and the second duty information and generate a second code;
an operator configured to divide the first code by the second code, and output a result of the division of the first code by the second code as a duty error determination code; and
a code comparison part configured to compare a stored reference code with the duty error determination code, and generate the noise detection signal.
10. A noise detection circuit comprising:
a divider configured to receive a clock signal and a clock bar signal, divide the clock signal and the clock bar signal, and generate a first divided signal and a second divided signal; and
a detection circuit configured to generate a noise detection signal with regards the first divided signal and the second divided signal.