PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR
A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.
1 . A thin film transistor (TFT), comprising:
a) a semiconductor thin film layer on a substrate, the semiconductor thin film layer including a channel region of the TFT;
b) at least part of a doped glass pattern on the semiconductor thin film layer, wherein the doped glass pattern includes a gap over the channel region of the TFT;
c) a gate electrode in the gap and on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon, and the gap defining at least one dimension of at least part of the gate electrode; and
d) dopant-containing regions in the semiconductor thin film layer on opposed sides of the channel region, wherein the dopant of the dopant-containing regions is identical to a dopant of the doped glass pattern.
2 . The TFT of claim 1 , comprising a plurality of the semiconductor thin film layers, in a transistor body pattern on the substrate.
3 . The TFT of claim 1 , wherein the semiconductor thin film layer includes source and drain regions on opposed sides of the channel region, and the doped glass pattern is on or over the source and drain regions of the semiconductor thin film layer.
4 . The TFT of claim 1 , wherein the gate dielectric film is on part of a surface of the semiconductor thin film layer other than in the gap.
5 . The TFT of claim 1 , wherein the gate electrode fills the gap.
6 . The TFT of claim 1 , wherein the gate dielectric film comprises a thermal oxide of the semiconductor thin film layer.
7 . The TFT of claim 1 , wherein the doped glass pattern is on the semiconductor thin film layer, and the gate dielectric film is only in the gap.
8 . The TFT of claim 1 , wherein the gate conductor comprises a metal.
9 . The TFT of claim 1 , wherein a concentration of the dopant of the dopant-containing regions is less than a concentration of the dopant of the doped glass pattern.
10 . The TFT of claim 1 , further comprising a plurality of openings in the doped glass pattern, exposing surfaces of the dopant-containing regions of the semiconductor thin film layer.
11 . The TFT of claim 1 , further comprising a conductive interconnect structure on the exposed surfaces of the dopant-containing regions of the semiconductor thin film layer.
12 . The TFT of claim 11 , further comprising an interlayer dielectric film over the doped glass pattern, the gate electrode and at least part of the conductive interconnect structure.
13 . The TFT of claim 1 , further comprising an interlayer dielectric film over the doped glass pattern and the gate electrode.
14 . The TFT of claim 13 , wherein the interlayer dielectric film has a different composition than the doped glass pattern.
15 . The TFT of claim 1 , further comprising a passivation layer on an exposed surface of the doped glass pattern.
16 . The TFT of claim 1 , further comprising a dopant-depleted layer in an exposed surface of the doped glass pattern.
17 . The TFT of claim 1 , wherein each interface between an individual dopant-containing region and the channel region is substantially aligned with an edge of the doped glass pattern.
18 . The TFT of claim 1 , wherein the gate conductor is on the doped glass pattern, outside of the gap.