System and method for recovering from a configuration error
View Patent ↗A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.
1. A method for recovering from errors in an information handling system, comprising:
enabling a progress monitoring process by a Basic Input Output System (BIOS);
determining, from the progress monitoring process, whether a first memory configuration error has occurred on the information handling system;
configuring a memory included in a node of a plurality of nodes of an information handling system, based on the determination of whether a first memory configuration error has occurred, wherein each of the nodes includes a processor;
disabling the memory based on a determination by the BIOS that a second memory configuration error has occurred with respect to the memory; and
modifying a memory reference code associated with the memory in order to prevent the information handling system from entering an infinite loop based on a reset of the information handling system in response to the second memory configuration error.
2. The method of claim 1 , further comprising:
determining whether a soft reboot occurred as a result of the first memory configuration error; and
configuring the memory further based on the determination of whether the soft reboot occurred as a result of the first memory configuration error.
3. The method of claim 1 , further comprising:
writing a first data pattern to the memory;
reading a second data pattern from the memory; and
determining whether the second data pattern matches the first data pattern.
4. The method of claim 3 , further comprising determining that the second memory configuration error occurred based on the determination of whether the second data pattern matches the first data pattern.
5. The method of claim 1 , further comprising setting a bit in a register associated with the memory in order to disable the memory.
6. The method of claim 1 , further comprising disabling the memory by excluding the memory from use by an operating system executing on the information handling system.
7. The method of claim 1 , further comprising:
enabling a memory configuration recovery process after the memory is disabled; and
overriding a failed status of the memory subsequent to disabling the memory.
8. An information handling system, comprising:
a processor; and
computer-readable media comprising instructions readable by the processor;
wherein the processor is to, when executing the instructions loaded from the computer-readable media:
enable a progress monitoring process by a Basic Input Output System (BIOS);
determine, from the progress monitoring process, whether a first memory configuration error has occurred on the information handling system;
configure a memory included in a node of a plurality of nodes of an information handling system, based on the determination of whether a first memory configuration error has occurred, wherein each of the nodes includes a node processor;
disable the memory based on a determination by the BIOS that a second memory configuration error has occurred with respect to the memory; and
modify a memory reference code associated with the memory in order to prevent the information handling system from entering an infinite loop based on a reset of the information handling system in response to the second memory configuration error.
9. The information handling system of claim 8 , wherein the processor is further to:
determine whether a soft reboot occurred as a result of the first memory configuration error; and
configure the memory further based on the determination of whether the soft reboot occurred as a result of the first memory configuration error.
10. The information handling system of claim 8 , wherein the processor is further to:
write a first data pattern to the memory;
read a second data pattern from the memory; and
determine whether the second data pattern matches the first data pattern.
11. The information handling system of claim 10 , wherein the processor is further to determine that the second memory configuration error occurred based on the determination of whether the second data pattern matches the first data pattern.
12. The information handling system of claim 8 , wherein the processor is further to set a bit in a register associated with the memory in order to disable the memory.
13. The information handling system of claim 8 , wherein the processor is further to disable the memory by excluding the memory from use by an operating system executing on the information handling system.
14. The information handling system of claim 8 , wherein the processor is further to:
enable a memory configuration recovery process after the memory is disabled; and
override a failed status of the memory subsequent to disabling the memory.
15. A non-transitory computer-readable media comprising instructions readable by a processor, the instructions, when loaded and executed on the processor, to cause the processor to:
enable a progress monitoring process by a Basic Input Output System (BIOS);
determine, from the progress monitoring process, whether a first memory configuration error has occurred on the information handling system;
configure a memory included in a node of a plurality of nodes of an information handling system, based on the determination of whether a first memory configuration error has occurred, wherein each of the nodes includes a node processor;
disable the memory based on a determination by the BIOS that a second memory configuration error has occurred with respect to the memory; and
modify a memory reference code associated with the memory in order to prevent the information handling system from entering an infinite loop based on a reset of the information handling system in response to the second memory configuration error.
16. The non-transitory computer-readable memory media of claim 15 , further comprising instructions for causing the processor to:
determine whether a soft reboot occurred as a result of the first memory configuration error; and
configure the memory further based on the determination of whether the soft reboot occurred as a result of the first memory configuration error.
17. The non-transitory computer-readable memory media of claim 15 , further comprising instructions for causing the processor to:
write a first data pattern to the memory;
read a second data pattern from the memory; and
determine whether the second data pattern matches the first data pattern.
18. The non-transitory computer-readable memory media of claim 17 , further comprising instructions for causing the processor to determine that the second memory configuration error occurred based on the determination of whether the second data pattern matches the first data pattern.
19. The non-transitory computer-readable memory media of claim 15 , further comprising instructions for causing the processor to set a bit in a register associated with the memory in order to disable the memory.
20. The non-transitory computer-readable memory media of claim 15 , further comprising instructions for causing the processor to:
enable a memory configuration recovery process after the memory is disabled; and
override a failed status of the memory subsequent to disabling the memory.