Controling Tx/Rx mode in serial half-duplex UART separately from host
Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the integrated circuit separately from a host processor of the integrated circuit with which the transceiver communicates. This can avoid slow transceiver turn-around times that may be associated with host processor control of the mode transitions.
1. An integrated circuit comprising:
a host processor;
serial, half-duplex, UART circuitry coupled to the host processor and having a receive data input and a transmit data output, the transmit data output being separate from the receive data output; and
logic circuitry that is separate from the host processor and the UART circuitry, the logic circuitry having a transmit data input coupled to the transmit data output and having a transmit/receive mode output.
2. The integrated circuit of claim 1 in which the logic circuitry includes co-processor circuitry.
3. The integrated circuit of claim 1 in which the logic circuitry includes timer circuitry coupled to the transmit data input and to the a transmit/receive mode output.
4. The integrated circuit of claim 1 in which the host processor is free of any transmit/receive mode output.
5. The integrated circuit of claim 1 including transceiver circuitry having a receive data output coupled to the receive data input, a transmit data input coupled to the transmit data output, and a mode input coupled to the transmit/receive mode output.
6. An integrated circuit comprising:
a host processor;
serial, half-duplex, UART circuitry coupled to the host processor and having a receive data input and a transmit data output, the transmit data output being separate from the receive data output, the UART circuitry including a line status register tracking progress of frame transmission on the transmit data output; and
logic circuitry that is separate from the host processor and the UART circuitry, the logic circuitry having a transmit data input coupled to the transmit data output, a transmit/receive mode output, and a line status register input coupled to the line status register of the UART circuitry.
7. The integrated circuit of claim 6 in which the logic circuitry includes co-processor circuitry.
8. The integrated circuit of claim 6 in which the host processor is free of any transmit/receive mode output.
9. The integrated circuit of claim 6 including transceiver circuitry having a receive data output coupled to the receive data input, a transmit data input coupled to the transmit data output, and a mode input coupled to the transmit/receive mode output.