IP Library Granted Patent US 10,297,712
Granted Patent B2
US 10,297,712 · App. 14/312,554 · Granted May 21, 2019

Micro LED display

Inventors: Andreas Bibl (Los Altos, CA); John A. Higginson (Santa Clara, CA); Hung-Fai Stephen Law (Los Altos, CA); Hsin-Hua Hu (Los Altos, CA)
Assignee: Apple Inc.
H01L33/06F21V7/00H01L27/15H01L29/0684H01L33/0079H01L33/04H01L33/28H01L33/30H01L25/0753H01L33/20H01L2224/95
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Quick Facts
Patent No.
US 10,297,712
App. No.
14/312,554
Granted
May 21, 2019
Kind
B2
Abstract

A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Claims (30)

1. A display substrate comprising:

a plurality of separate micro LED devices bonded to a corresponding plurality of separate driver contacts; and

a common contact line formed of a transparent material directly over and in electrical contact with a top surface of each of the plurality of separate micro LED devices, wherein each of the plurality of separate micro LED devices comprises:

a p-n diode including:

a bottom surface directly beneath the top surface;

a p-doped layer;

an n-doped layer; and

a quantum well layer between the n-doped layer and the p-doped layer;

wherein the p-n diode is less than 3 μm thick and less than 10 μm wide; and

a lower metallization layer including a top surface and a bottom surface, wherein the top surface of the lower metallization layer is underneath the bottom surface of the p-n diode, and the bottom surface of the lower metallization layer is directly over and bonded to a corresponding driver contact;

wherein a maximum thickness between the top surface of the p-n diode and the bottom surface of the lower metallization layer is less than 5 μm.

2. The display substrate of claim 1 , wherein the common contact line comprises indium tin oxide.

3. The display substrate of claim 1 , further comprising a plurality of separate bonding layers, wherein each lower metallization layer is bonded to a corresponding driver contact with a corresponding bonding layer.

4. The display substrate of claim 3 , wherein each bonding layer comprises indium.

5. The display substrate of claim 1 , wherein each p-n diode has a square configuration with tapered corners.

6. The display substrate of claim 1 , further comprising a plurality of dielectric barrier layers, wherein each dielectric barrier layer spans sidewalls of a corresponding p-n diode.

7. The display substrate of claim 6 , wherein each dielectric barrier layer covers the quantum well layer of a corresponding p-n diode.

8. The display substrate of claim 7 , wherein common contact line is on each dielectric barrier layer, such that each dielectric barrier layer electrically insulates a corresponding quantum well from the common contact line.

9. The display substrate of claim 8 , wherein the plurality of separate micro LED devices are arranged in a pixel group.

10. The display substrate of claim 9 , wherein the pixel group includes a red-emitting micro LED device, a green-emitting micro LED device, and a blue-emitting micro LED device.

11. The display substrate of claim 1 , wherein the p-doped layer is thinner than the n-doped layer.

12. The display substrate of claim 1 , wherein the p-n diode comprises an inorganic II-VI or III-V semiconductor.

13. The display substrate of claim 1 , wherein the top and bottom surface of each p-n diode are concentric.

14. The display substrate of claim 13 , wherein the top and bottom surface of each p-n diode are parallel.

15. The display substrate of claim 14 , wherein the top surface of each p-n diode is planar.

16. The display substrate of claim 15 , wherein the bottom surface of each p-n diode is wider than a corresponding lower metallization layer.

17. The display substrate of claim 13 , wherein the bottom surface of each p-n diode is wider than a corresponding lower metallization layer.

18. The display substrate of claim 1 , wherein the plurality of separate micro LED devices are arranged in a pixel group.

19. The display substrate of claim 1 , wherein the plurality of separate micro LED devices are arranged in a pixel group.

20. The display substrate of claim 19 , wherein the pixel group includes micro LED devices that are designed to emit different colors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2016
From: LUXVUE TECHNOLOGY CORPORATION
To: APPLE INC.
Reel/Frame 038521/0255 →
Continuity (4)
Continuation 13372258 · Feb 13, 2012
Provisional Application 61561706 · Nov 18, 2011
Provisional Application 61594919 · Feb 3, 2012
Related Publication 20140299837A1 · Oct 9, 2014
Cited By (3)
US 12,243,955 US 12,582,767 US 12,593,556