Linear to physical address translation with support for page attributes
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
1. A processor comprising:
a plurality of registers;
at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;
a page miss handler to perform a table walk; and
a physical address return register, wherein the physical address return register is a 64-bit register,
wherein the processor is to receive an instruction to translate a virtual address to a first physical address, wherein the instruction is a kernel level privileged instruction, and
wherein the instruction is to cause the processor, when in a 64-bit mode, to:
translate the virtual address to the first physical address;
store the first physical address translated from the virtual address in the physical address return register; and
store at least one attribute associated with the first physical address translated from the virtual address in the physical address return register.
2. The processor of claim 1 , wherein the at least one attribute comprises an indication of whether a fault occurred during the translation of the virtual address to the first physical address.
3. The processor of claim 1 , wherein the at least one attribute comprises a caching policy indication.
4. The processor of claim 1 , wherein the at least one attribute comprises a protection level.
5. The processor of claim 1 , wherein the instruction is to cause the processor to translate the virtual address to the first physical address as if a write is performed for the instruction.
6. The processor of claim 1 , wherein the physical address return register is a register dedicated to storing physical addresses and associated attributes.
7. The processor of claim 1 , wherein the instruction is to operate at a higher privilege level than an application.
8. The processor of claim 1 , wherein the instruction is to cause the processor to translate the virtual address to the first physical address without accessing data at the first physical address in a memory hierarchy.
9. A processor comprising:
a plurality of registers;
at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;
a page miss handler to perform a table walk; and
a physical address return register, wherein the physical address return register is a 64-bit register,
wherein the processor is to receive an instruction to translate a virtual address to a first physical address, wherein the instruction is a kernel level privileged instruction, and
wherein the instruction is to cause the processor, when in a 64-bit mode, to:
start to translate the virtual address to the first physical address;
store an indication that a fault occurred in the physical address return register; and
store a level at which the fault occurred in the physical address return register.
10. The processor of claim 9 , wherein the instruction is to cause the processor not to take an exception when the fault occurred.
11. The processor of claim 9 , wherein the physical address return register is a register dedicated to storing a physical address translated from a virtual address.
12. The processor of claim 9 , wherein the instruction is to cause the processor to start to translate the virtual address to the first physical address as if a write is to be performed for the instruction.
13. The processor of claim 9 , wherein the instruction is to operate at a higher privilege level than applications.