Eight transistor soft error robust storage cell
View Patent ↗A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.
1. A circuit comprising:
a storage cell including:
a plurality of transistors; and
at least four storage nodes formed between the plurality of transistors, wherein each of the storage nodes is configured to change states;
wherein:
each of the at least four storage nodes is connected to two gates of the plurality of transistors; and
at least one of: only two of the plurality of transistors are connected to V DD or only two of the plurality of transistors are connected to ground.
2. The circuit of claim 1 , wherein only two of the plurality of transistors are connected to V DD .
3. The circuit of claim 1 , wherein only two of the plurality of transistors are connected to ground.
4. The circuit of claim 1 , wherein:
only two of the plurality of transistors are connected to V DD ;
only two of the plurality of transistors are connected to ground;
a first storage node of the at least four storage nodes is electrically connected to a gate of a first transistor of the only two of the plurality of transistors connected to V DD ;
the first storage node is electrically connected to a gate of a first transistor of the only two of the plurality of transistors connected to ground;
a second storage node of the at least four storage nodes is electrically connected to a gate of a second transistor of the only two of the plurality of transistors connected to V DD ; and
the second storage node is electrically connected to a gate of a second transistor of the only two of the plurality of transistors connected to ground.
5. The circuit of claim 4 , wherein:
a third storage node of the at least four storage nodes is electrically connected to a drain of a first transistor of the only two of the plurality of transistors connected to V DD ;
the third storage node is electrically connected to a drain of a first transistor of the only two of the plurality of transistors connected to ground;
a fourth storage node of the at least four storage nodes is electrically connected to a drain of a second transistor of the only two of the plurality of transistors connected to V DD ; and
the fourth storage node is electrically connected to a drain of a second transistor of the only two of the plurality of transistors connected to ground.
6. The circuit of claim 1 , wherein the at least four storage nodes comprise only four storage nodes.
7. The circuit of claim 1 , wherein the circuit is configured such that a soft error on only one of the at least four storage nodes will be automatically corrected.
8. The circuit of claim 1 , wherein the circuit is included in a flip-flop circuit.
9. The circuit of claim 1 , wherein:
only two of the plurality of transistors are connected to V DD ;
a first storage node of the at least four storage nodes is electrically connected to a gate of a first transistor of the only two of the plurality of transistors connected to V DD ; and
a second storage node of the at least four storage nodes is electrically connected to a gate of a second transistor of the only two of the plurality of transistors connected to V DD .
10. The circuit of claim 9 , wherein:
a third storage node of the at least four storage nodes is electrically connected to a drain of a first transistor of the only two of the plurality of transistors connected to V DD ; and
a fourth storage node of the at least four storage nodes is electrically connected to a drain of a second transistor of the only two of the plurality of transistors connected to V DD .
11. The circuit of claim 1 , wherein:
only two of the plurality of transistors are connected to ground;
a first storage node of the at least four storage nodes is electrically connected to a gate of a first transistor of the only two of the plurality of transistors connected to ground; and
a second storage node of the at least four storage nodes is electrically connected to a gate of a second transistor of the only two of the plurality of transistors connected to ground.
12. The circuit of claim 11 , wherein:
a third storage node of the at least four storage nodes is electrically connected to a drain of a first transistor of the only two of the plurality of transistors connected to ground; and
a fourth storage node of the at least four storage nodes is electrically connected to a drain of a second transistor of the only two of the plurality of transistors connected to ground.
13. The circuit of claim 1 , wherein:
only two of the plurality of transistors are connected to V DD ; and
only two of the plurality of transistors are connected to ground.
14. The circuit of claim 1 , wherein:
the plurality of transistors comprise a plurality of NMOS transistors and a plurality of PMOS transistors;
each of the at least four storage nodes is connected to a gate of a different NMOS transistor in the plurality of NMOS transistors; and
each of the at least four storage nodes is connected to a gate of a different PMOS transistor in the plurality of PMOS transistors.