IP Library Granted Patent US 9,697,831
Granted Patent B2
US 9,697,831 · App. 14/314,182 · Granted Jul 4, 2017

Speech recognition

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Quick Facts
Patent No.
US 9,697,831
App. No.
14/314,182
Granted
Jul 4, 2017
Kind
B2
Abstract

A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.

Claims (22)

1. A speech processing system comprising;

an input for receiving an input signal from at least one microphone;

a first signal path for connecting the input to an output;

a second signal path for connecting the input to the output;

selection circuitry for selecting either the first signal path or the second signal path for carrying the input signal from the input to the output; wherein:

the first signal path contains a first buffer for storing the input signal;

the second signal path contains a noise reduction block for receiving the input signal and supplying a noise reduced signal to the output, and a second buffer; wherein:

the second buffer imparts a delay in the second signal path such that the noise reduced signal is substantially time-aligned with the output of the first buffer; and

a signal activity detection block for detecting if the input signal contains speech, wherein the first buffer comprises:

a first part which is continuously buffering; and

a second part which only starts buffering after the signal activity detection block detects that the input signal contains speech.

2. An integrated circuit comprising a speech recognition system as claimed in claim 1 .

3. A communications device comprising an integrated circuit as claimed in claim 2 .

4. A method for speech recognition comprising:

receiving an input signal from at least one microphone;

selecting either a first signal path or a second signal path for carrying the input signal to the output; wherein:

the first signal path contains a first buffer for storing the input signal; and

the second signal path contains a noise reduction block for receiving the input signal and supplying a noise reduced signal to the output, and a second buffer; wherein:

the second buffer imparts a delay in the second signal path such that the noise reduced signal is substantially time-aligned with the output of the first buffer; and

detecting if the input signal contains speech, wherein the first buffer comprises:

a first part which is continuously buffering; and

a second part which only starts buffering after the signal activity detection block detects that the input signal contains speech.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2017
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 042520/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2015
From: CIRRUS LOGIC INTERNATIONAL (UK) LTD.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 035806/0389 →
CHANGE OF NAME Recorded Apr 1, 2015
From: WOLFSON MICROELECTRONICS PLC
To: WOLFSON MICROELECTRONICS LTD
Reel/Frame 035353/0409 →
CHANGE OF NAME Recorded Apr 1, 2015
From: WOLFSON MICROELECTRONICS LTD
To: CIRRUS LOGIC INTERNATIONAL (UK) LTD.
Reel/Frame 035353/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2014
From: LESSO, JOHN PAUL; HATFIELD, ROBERT JAMES
To: WOLFSON MICROELECTRONICS PLC
Reel/Frame 033173/0764 →