Control circuit for active-clamp flyback power converter with programmable switching period
A method for controlling an active-clamp flyback power converter is provided. The method includes comprises: generating a switching signal in response to a feedback signal for switching a low-side transistor and regulating an output of the active-clamp flyback power converter; generating an active-clamp signal after the switching signal is disabled; generating a hysteresis bias to adjust the feedback signal; and generating a pulse signal periodically to enable the switching signal. The low-side transistor is coupled to switch a transformer. The switching signal is coupled to drive the low-side transistor. The active-clamp signal is coupled to drive a high-side transistor. A pulse width of the active-clamp signal is determined by a first resistor. The high-side transistor is connected in series with a capacitor to develop an active-clamp circuit. A minimum frequency of the switching signal is determined by a second resistor during a heavy load condition.
1. A control circuit of an active-clamp flyback power converter comprising:
a low-side transistor coupled to switch a transformer;
a high-side transistor connected in series with a capacitor to develop an active-clamp circuit, wherein said active-clamp circuit is coupled in parallel with said transformer;
a high-side driving circuit coupled to drive said high-side transistor; and
a controller generating a switching signal and an active-clamp signal,
wherein said switching signal is coupled to drive said low-side transistor, and said switching signal is generated in response to a feedback signal for regulating an output of said active-clamp flyback power converter, and
wherein said active-clamp signal is coupled to said high-side driving circuit for controlling said high-side transistor, said active-clamp signal comprises a pulse having a rising edge and a falling edge, and a time point of said falling edge is determined by a first resistor.
2. The control circuit as claimed in claim 1 , wherein said active-clamp signal is enabled after said switching signal is disabled, and said switching signal can be enabled after said active-clamp signal is disabled.
3. The control circuit as claimed in claim 1 , wherein a minimum frequency of said switching signal is determined by a second resistor during a heavy load condition.
4. The control circuit as claimed in claim 1 , wherein the controller comprises:
a hysteresis bias generator for generating a hysteresis bias to adjust said feedback signal; and
a comparator having a light-load threshold to control said hysteresis bias,
wherein said comparator controls said hysteresis bias in response to a value of said feedback signal and said light-load threshold.
5. The control circuit as claimed in claim 1 , wherein said switching signal will be enabled in response to a pulse signal, and said pulse signal is generated periodically by an oscillation circuit of said controller.
6. The control circuit as claimed in claim 1 further comprising a charge-pump circuit, wherein the charge-pump circuit comprises:
a diode coupled to a supply voltage; and
a charge-pump capacitor coupled to said diode in series;
wherein said charge-pump capacitor is connected to said high-side driving circuit.
7. A method for controlling an active-clamp flyback power converter comprising:
generating a switching signal in response to a feedback signal for switching a low-side transistor and regulating an output of said active-clamp flyback power converter; and
generating an active-clamp signal after said switching signal is disabled;
wherein said low-side transistor is coupled to switch a transformer, and said switching signal is coupled to drive said low-side transistor,
wherein said active-clamp signal is coupled to drive a high-side transistor, said active-clamp signal comprises a pulse having a rising edge and a falling edge, and a time point of said falling edge is determined by a first resistor, and
wherein said high-side transistor is connected in series with a capacitor to develop an active-clamp circuit, and the active-clamp circuit is coupled in parallel with said transformer.
8. The method as claimed in claim 7 , wherein said active-clamp signal is enabled after said switching signal is disabled, and said switching signal is enabled after said active-clamp signal is disabled.
9. The method as claimed in claim 7 , wherein a minimum frequency of said switching signal is determined by a second resistor during a heavy load condition.
10. The method as claimed in claim 7 further comprising:
generating a hysteresis bias to adjust said feedback signal,
wherein said hysteresis bias is generated in response to a value of said feedback signal and a light-load threshold.
11. The method as claimed in claim 7 further comprising:
generating a pulse signal periodically to enable said switching signal.
12. The method as claimed in claim 11 , wherein said pulse signal is coupled to determine a maximum on-time of said switching signal.