Transactional memory operations with read-only atomicity

1. A computer system for performing transactional memory operations in a multi-processor transactional execution (TX) environment, the system comprising:

a memory; and

a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:

executing, by the processor, an instruction to cause a transaction be executed in an atomic read-only transaction mode, execution in the atomic read-only transaction mode comprising:

tracking, by the processor, memory read accesses as a read-set of the transaction;

based on detecting, by the processor, a read-set conflict, aborting the transaction;

suppressing, by the processor, any transaction abort due to conflicts of a write-set generated while in the atomic read-only transaction mode; and

absent any aborting, completing the transaction, by the processor, the completing comprising committing stores executed in the transaction to memory and updating architecture states,

wherein the write-set is tracked with dirty bits while inside the read-only mode, wherein each dirty bit is associated with a read-only indicator, the read-only indicator indicating that any conflict detected with the write-set should be ignored.

2. The system of claim 1 , wherein the instruction is an enter TX read-only mode instruction that signals any one of:

a beginning of the transaction, wherein executing the instruction causes the transaction to be started and executed, by the processor, in the atomic read-only transaction mode;

a beginning of the atomic read-only transaction mode, wherein a preceding instruction causes the transaction to be started, by the processor, in a mode other than the atomic read-only transaction mode; and

a resuming of the atomic read-only transaction mode, wherein executing a preceding instruction, by the processor, suspends the atomic read-only transaction mode.

3. The system of claim 1 , wherein the atomic read-only transaction mode is reset based upon any one or more of:

a completion of execution of a number of instructions specified by the instruction;

execution of a resetting instruction; and

an ending of the transaction.

4. The system of claim 1 , the method further comprising:

suppressing a corresponding storage update from being committed at a successful ending of the transaction, upon detecting a conflict with the write-set, wherein the read-only indicators of the write-set are active.

5. The system of claim 1 , the method further comprising: committing, by the processor, a write-set of the transaction having corresponding read-only indicators active upon detecting a conflict, without waiting for the transaction to end successfully.

6. The system of claim 1 , the method further comprising:

executing, by the processor, an immediately preceding prefix instruction signaling to the instruction to begin execution of the transaction in the atomic read-only transaction mode.

7. A computer program product for performing transactional memory operations in a multi-processor transactional execution (TX) environment, the computer program product comprising: a computer-readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising:

executing, by the processing circuit, an instruction to cause a transaction be executed in an atomic read-only transaction mode, execution in the atomic read-only transaction mode comprising:

tracking, by the processing circuit, memory read accesses as a read-set of the transaction;

based on detecting a read-set conflict, aborting, by the processing circuit, the transaction;

suppressing, by the processing circuit, any transaction abort due to conflicts of a write-set generated while in the atomic read-only transaction mode; and

absent any aborting, completing the transaction, the completing comprising committing, by the processing circuit, stores executed in the transaction to memory and updating architecture states,

wherein the write-set is tracked, by the processing circuit, with dirty bits while inside the read-only mode, wherein each dirty bit is associated with a read-only indicator, the read-only indicator indicating that any conflict detected with the write-set should be ignored.

8. The computer program product of claim 7 , wherein the instruction is an enter TX read-only mode instruction that signals any one of:

a beginning of the transaction, wherein executing the instruction causes the transaction to be started and executed, by the processing circuit, in the atomic read-only transaction mode;

a beginning of the atomic read-only transaction mode, wherein a preceding instruction causes the transaction to be started, by the processing circuit, in a mode other than the atomic read-only transaction mode; and

a resuming of the atomic read-only transaction mode, wherein executing a preceding instruction, by the processing circuit, suspends the atomic read-only transaction mode.

9. The computer program product of claim 7 , wherein the atomic read-only transaction mode is reset, by the processing circuit, based upon any one or more of:

a completion of execution of a number of instructions specified by the instruction;

execution of a resetting instruction; and

an ending of the transaction.

10. The computer program product of claim 7 , the method further comprising:

suppressing, by the processing unit, a corresponding storage update from being committed at a successful ending of the transaction, upon detecting a conflict with the write-set, wherein the read-only indicator bits of the write-set are active.

11. The computer program product of claim 7 , the method further comprising: committing, by the processing circuit, a write-set of the transaction having corresponding read-only indicator bits active upon detecting a conflict, without waiting for the transaction to end successfully.

12. The computer program product of claim 7 , the method further comprising:

executing, by the processing circuit, an immediately preceding prefix instruction signaling to the instruction to begin execution of the transaction in the atomic read-only transaction mode.