IP Library Granted Patent US 9,501,418
Granted Patent B2
US 9,501,418 · App. 14/316,256 · Granted Nov 22, 2016

Invalidation data area for cache

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Quick Facts
Patent No.
US 9,501,418
App. No.
14/316,256
Granted
Nov 22, 2016
Kind
B2
Abstract

The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.

Claims (15)

1. A cache comprising:

a journal configured for tracking data blocks stored in the cache; and

an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal, wherein the invalidation data area is on a separate region of the cache from the journal;

wherein the journal is configured for tracking metadata for the data blocks, and wherein the metadata comprises a memory address corresponding to the data block,

wherein the invalidation data area is configured for tracking metadata associated with the invalidated data blocks, and wherein the associated metadata comprises a memory address corresponding to the invalidated data block,

wherein the memory address tracked in the invalidation data area is truncated compared to the memory address tracked in the journal, based on at least one of a storage size of an underlying storage device being cached and an offset determined based on a memory address of a block in the underlying storage device.

2. The cache of claim 1 ,

wherein the journal is configured for tracking the data blocks using journal blocks, wherein the journal blocks are configured for storing the metadata for the data blocks; and

wherein the invalidation data area is configured for tracking the metadata associated with the invalid data blocks using invalidation records and mapped journal blocks, wherein the mapped journal blocks are configured for storing the associated metadata for the invalid data blocks, and wherein the invalidation records are configured for storing the mapped journal blocks.

3. The cache of claim 2 ,

wherein the metadata tracked in the journal further comprises an index into a collection of metadata stored in each journal block, and

wherein the metadata tracked in the invalidation data area further comprises an index into a collection of metadata stored in each mapped journal block.

4. The cache of claim 3 , wherein the index tracked in the journal is selected to have the same value as the index tracked in the invalidation data area.

5. The cache of claim 2 , wherein the cache is configured to determine an invalidation record number associated with an invalidation record in the invalidation data area based on a corresponding journal block number associated with a journal block.

6. The cache of claim 2 , wherein the cache is configured to determine a mapped journal block number associated with a mapped journal block in the invalidation area based on a corresponding journal block number associated with a journal block.

Assignments (6)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040829/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2015
From: MISRA, PULKIT
To: HGST NETHERLANDS B.V.
Reel/Frame 035666/0878 →