Mesh grid protection system

1. A grid protection system in an integrated circuit chip, the grid protection system comprising:

a first sector including a first set of grid lines;

a second sector including a second set of grid lines at a lower layer of the integrated circuit chip than the first set of grid lines;

assertion logic configured to transmit a first set of signals on the first set of grid lines and the second set of grid lines;

transformation logic, coupled to the first and the second sets of grid lines, the transformation logic configured to transform the first set of signals to a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines; and

verification logic, coupled to the transformation logic, configured to compare the second set of signals on the third and the fourth sets of grid lines to an expected set of signals.

2. The grid protection system of claim 1 , wherein the verification logic is further configured to generate a signal to indicate a breach of the grid protection system based on the comparison of the second set of signals on the third and fourth set of grid lines to the expected set of signals.

3. The grid protection system of claim 1 , wherein the verification logic is further configured to generate the expected set of signals.

4. The grid protection system of claim 1 , wherein an expected signal from the expected set of signals for a first grid line of the third set of grid lines is on a second grid line of the third set of grid lines.

5. The grid protection system of claim 1 , wherein the transformation logic is further configured to transform the first set of signals based on a random number.

6. The grid protection system of claim 5 , wherein the random number is changed periodically or at random time intervals.

7. The grid protection system of claim 1 , wherein the transformation logic comprises at least one of: a substitution box (s-box), a permutation box (p-box), a substitution and permutation box (sp-box), or a cryptographic algorithm.

8. A method in an integrated circuit chip, the method comprising:

transmitting a first set of signals on a first set of grid lines;

transmitting the first set of signals on a second set of grid lines that are at a lower layer of the integrated circuit chip than the first set of grid lines;

transforming the first set of signals to a second set of signals;

transmitting the second set of signals on a third set of grid lines that are coupled to the first set of grid lines;

transmitting the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines; and

comparing the transmitted second set of signals on the third and the fourth sets of grid lines to an expected set of signals.

9. The method of claim 8 , further comprising:

generating a signal to indicate whether there is an attempt to access operational logic based on the comparing.

10. The method of claim 8 , wherein an expected signal from the expected set of signals for a first grid line of the third set of grid lines is on a second grid line of the third set of grid lines.

11. The method of claim 8 , further comprising:

generating the expected set of signals prior to the comparing.

12. The method of claim 8 , wherein the transforming comprises:

transforming the first set of signals based on a random number.

13. The method of claim 12 , further comprising:

changing the random number periodically or at random time intervals.

14. The method of claim 8 , wherein the transforming comprises:

transforming the first set of signals using at least one of: a substitution box (s-box), a permutation box (p-box), a substitution and permutation box (sp-box), or a cryptographic algorithm.

15. A grid protection system in an integrated circuit, the grid protection system comprising:

a processor;

a memory, coupled to the processor, configured to store instructions that, when executed by the processor, cause the processor to:

transmit a first set of signals on a first set of grid lines;

transmit the first set of signals on a second set of grid lines that are at a lower layer of the integrated circuit chip than the first set of grid lines;

receive the first set of signals;

transform the first set of signals to a second set of signals;

transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines;

transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines; and

compare the transmitted second set of signals on the third and the fourth sets of grid lines to an expected set of signals.

16. The grid protection system of claim 15 , wherein the instructions, that when executed by the processor, further cause the processor to generate a signal to indicate whether there is an attempt to access operational logic based on the comparison.

17. The grid protection system of claim 15 , wherein the expected set of signals for a first grid line of the third set of grid lines is on a second grid line of the third set of grid lines.

18. The grid protection system of claim 15 , wherein the instructions, that when executed by the processor, further cause the processor to generate the expected set of signals prior to the comparison.

19. The grid protection system of claim 15 , wherein the instructions, that when executed by the processor, further cause the processor to transform the first set of signals based on a random number.

20. The grid protection system of claim 19 , wherein the instructions, that when executed by the processor, further cause the processor to change the random number periodically or at random time intervals.