IP Library Granted Patent US 9,251,845
Granted Patent B2
US 9,251,845 · App. 14/318,665 · Granted Feb 2, 2016

Multi-level enumerative encoder and decoder

Inventors: Victor Krachkovsky (Allentown, PA); Razmik Karabed (San Jose, CA); Shaohua Yang (San Jose, CA); Wu Chang (Sunnyvale, CA)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G11B20/1217
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Quick Facts
Patent No.
US 9,251,845
App. No.
14/318,665
Granted
Feb 2, 2016
Kind
B2
Abstract

A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

Claims (34)

1. A storage system comprising:

a storage medium operable to maintain a data set;

a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium;

a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases; and

a multi-level enumerative decoder operable to decode the data set after it is read from the storage medium.

2. The storage system of claim 1 , wherein the multi-level enumerative encoder is operable to determine a level number based at least in part on a cost-balance equation.

3. The storage system of claim 1 , wherein the multi-level enumerative encoder is operable to determine a level number based at least in part on a count of successive transitions in the encoded data.

4. The storage system of claim 1 , wherein the multi-level enumerative encoder further comprises a latency cancellation circuit, comprising a prohibited pattern detector operable to detect at least one prohibited pattern in the data set and a first sync pattern generator operable to generate a first sync pattern to replace the at least one prohibited pattern in the encoded data corresponding to a segment in the data set containing the prohibited pattern.

5. The storage system of claim 4 , wherein the first sync pattern comprises a level number determined by the multi-level enumerative encoder.

6. The storage system of claim 4 , wherein the first sync pattern comprises a count of successive transitions in the encoded data.

7. The storage system of claim 1 , wherein the multi-level enumerative encoder further comprises a k-constraint circuit, comprising a zero-run detector operable to detect runs of zero's in the encoded data and a second sync pattern generator operable to generate a second sync pattern to replace the runs of zero's in the encoded data.

8. The storage system of claim 1 , wherein the bases in the multi-level enumerative encoder comprise floating point representations with periodic mantissas.

9. The storage system of claim 8 , wherein the multi-level enumerative encoder applies level-dependent scaling to the bases.

10. The storage system of claim 1 , wherein the multi-level enumerative encoder and the multi-level enumerative decoder are operable to encode and to decode in a same bit-significance direction.

11. The storage system of claim 1 , wherein the multi-level enumerative encoder is operable to apply an extended maximum transition run constraint to the encoded data limiting a length of successive runs of transitions.

12. The storage system of claim 11 , wherein the extended maximum transition run constraint comprises a limit on a number of successive MTR- 3 runs of transitions.

13. A multi-level enumerative encoder comprising:

an encoder state circuit operable to store a state of the multi-level enumerative encoder;

a base lookup table operable to store a plurality of bases and to yield one of the plurality of bases according to an encoding level in the multi-level enumerative encoder;

a transition counter operable to generate a count of successive transitions in encoded data from the multi-level enumerative encoder;

a level generator operable to determine the encoding level in the multi-level enumerative encoder based at least in part on the count of successive transitions; and

a shift generator operable to shift input bits into the multi-level enumerative encoder based at least in part on the encoding level.

14. The multi-level enumerative encoder of claim 13 , wherein the plurality of bases comprise floating point representations with periodic mantissas.

15. The multi-level enumerative encoder of claim 13 , wherein the level generator is operable to determine the encoding level in the multi-level enumerative encoder based at least in part on a cost balance of encoded bits.

16. The multi-level enumerative encoder of claim 13 , further comprising a latency cancellation circuit, comprising a prohibited pattern detector operable to detect at least one prohibited pattern in the data to be encoded, and a first sync pattern generator operable to generate a first sync pattern to replace the at least one prohibited pattern in the encoded data corresponding to a segment in the data to be encoded that contains the prohibited pattern.

17. The multi-level enumerative encoder of claim 16 , wherein the first sync pattern comprises the encoding level.

18. The multi-level enumerative encoder of claim 16 , wherein the first sync pattern comprises the count of successive transitions.

19. A multi-level enumerative decoder comprising:

a first sync pattern detector operable to detect a first sync pattern in encoded data;

a level generator operable to determine a decoding level from among a plurality of decoding levels based on the first sync pattern;

a base lookup table operable to store a plurality of bases and to yield one of the plurality of bases according to the decoding level;

a shift circuit operable to shift said one of the plurality of bases based on the decoding level to yield a shifted base; and

a decoder state circuit operable to store a decoder state updated based on the shifted base and to shift out decoded bits.

20. The multi-level enumerative decoder of claim 19 , further comprising a second sync pattern detector operable to detect a second sync pattern in the encoded data, a zero run generator and a replacement circuit operable to replace the second sync pattern with a zero run in the encoded data.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
RELEASE OF SECURITY INTEREST Recorded Dec 10, 2019
From: VENTURE LENDING & LEASING VII, INC.; VENTURE LENDING & LEASING VIII, INC.
To: PLAYSTUDIOS, INC.
Reel/Frame 051237/0697 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
SECURITY INTEREST Recorded Oct 25, 2016
From: PLAYSTUDIOS, INC.
To: VENTURE LENDING & LEASING VII, INC.; VENTURE LENDING & LEASING VIII, INC.
Reel/Frame 040478/0844 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2014
From: KRACHKOVSKY, VICTOR; KARABED, RAZMIK; YANG, SHAOHUA; CHANG, WU
To: LSI CORPORATION
Reel/Frame 033605/0328 →
Continuity (1)
Related Publication 20150380050A1 · Dec 31, 2015