Programming memory cells dependent upon distortion estimation
A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines. Data is stored in one or more memory cells of the array using one or more programming levels. In response to a determination that a first memory cell of the one or more memory cells is subject to distortion, a second memory cell may be programmed to a predetermined programming level.
1. An apparatus, comprising:
a memory including a plurality of multi-level cells for data storage;
storage circuitry coupled to the memory, wherein the storage circuitry is configured to:
receive data for storage in the memory;
store the received data in one or more of the plurality of multi-level cells using one or more programming levels of a plurality of programming levels;
determine that at least a first multi-level cell is subject to distortion; and
program a second multi-level cell with a predetermined programming level in response to determining the first multi-level cell is subject to distortion, wherein the predetermined programming level is different than each programming level of the plurality of programming levels, wherein the predetermined programming level is indicative that the first multi-level cell is subject to distortion.
2. The apparatus of claim 1 , wherein the plurality of multi-level cells is arranged in a plurality of rows, wherein each row of the plurality of rows is associated with a respective word line.
3. The apparatus according to claim 2 , wherein the second multi-level cell is associated with a common wordline associated with the first multi-level cell.
4. The apparatus according to claim 2 , wherein the second multi-level cell is associated with another wordline, adjacent to a wordline associated with the first multi-level cell.
5. The apparatus according to claim 1 , wherein the storage circuitry is further configured to utilize the predetermined programming level to program one or more selected multi-level cells, including the second multi-level cell, solely to indicate that one or more associated multi-level cells, including the first multi-level cell, is subject to distortion.
6. The apparatus according to claim 1 , wherein the distortion includes disturb noise from multi-level cells adjacent to the first multi-level cell.
7. The apparatus according to claim 1 , wherein to determine that at least the first multi-level cell is subject to distortion, the storage circuitry is further configured to determine that at least the first multi-level cell is stuck at a given programming level.
8. A method for data storage, comprising:
receiving data for storage in a memory, wherein the memory includes a plurality of multi-level cells for data storage;
storing the received data in one or more multi-level cells using one or more programming levels of a plurality of programming levels;
determining at least a first multi-level cell is subject to distortion; and
programming a second multi-level cell with a predetermined programming level responsive to determining the first multi-level cell is subject to distortion, wherein the predetermined programming level is different than each programming level of the plurality of programming levels, wherein the predetermined programming level is indicative that the first multi-level cell is subject to distortion.
9. The method according to claim 8 , wherein the plurality of multi-level cells is arranged in a plurality of rows, wherein each row of the plurality of rows is associated with a respective word lines.
10. The method according to claim 9 , wherein the second multi-level cell is associated with a common wordline associated with the first multi-level cell.
11. The method according to claim 9 , wherein the second multi-level cell is associated with another wordline, adjacent to a wordline associated with the first multi-level cell.
12. The method according to claim 8 , further comprising utilizing the predetermined programming level to program one or more selected multi-level cells, including the second multi-level cell, solely to indicate that one or more associated multi-level cells, including the first multi-level cell, is subject to distortion.
13. The method according to claim 8 , wherein determining that at least the first multi-level cell is subject to distortion comprises determining that at least the first multi-level cell is stuck at a given programming level.
14. The method according to claim 8 , wherein distortion includes over-programming of the first multi-level cell.
15. A system comprising:
a memory device including a plurality of multi-level cells for data storage, wherein the plurality of multi-level cells is arranged in a plurality of rows, and wherein each row of the plurality of rows is associated with a respective word line; and
a host configured to send data for storage in the memory device;
wherein the memory device is configured to:
receive the data for storage in one or more of the plurality of multi-level cells;
store the received data in the one or more of the plurality of multi-level cells using one or more programming levels of a plurality of programming levels; and
program a second multi-level cell with a predetermined programming level responsive to determining a first multi-level cell is subject to distortion, wherein the predetermined programming level is different than each programming level of the plurality of programming levels, wherein the predetermined programming level is indicative that the first multi-level cell is subject to distortion.
16. The system according to claim 15 , wherein the second multi-level cell is associated with a common wordline associated with the first multi-level cell.
17. The system according to claim 15 , wherein the second multi-level cell is associated with another wordline, adjacent to a wordline associated with the first multi-level cell.
18. The system according to claim 15 , wherein the memory device is further configured to utilize the predetermined programming level to program one or more selected multi-level cells, including the second multi-level cell, solely to indicate that one or more associated multi-level cells, including the first multi-level cell, is subject to distortion.
19. The system according to claim 15 , wherein distortion includes over-programming of the first multi-level cell.
20. The system according to claim 15 , wherein to determine that at least the first multi-level cell is subject to distortion, the memory device is further configured to determine that at least the first multi-level cell is stuck at a given programming level.