Differential-to-single-end converter
A converter that converts a differential input signal to a single-end output signal is provided. The converter includes first, second, third and fourth transistors, and a pair of current sources. The first and second transistors are driven by the differential input signal, and have two conduction nodes coupled to each other and two conduction nodes not coupled to each other. The third and fourth transistors are driven by the differential input signal, and are connected in series with the first and second transistors. The pair of current sources, respectively connected in series with the third and fourth transistors, have a common control node coupled to the second conduction node of the first transistor. The second conduction node of the second transistor generates the single-end output signal.
1. A converter, for converting a differential input signal to a single-end output signal, comprising:
a first transistor and a second transistor, driven by the differential input signal, the first and second transistors having two first conduction nodes coupled to each other and two second conduction nodes not coupled to each other;
a third transistor and a fourth transistor, driven by the differential input signal, respectively connected in series with the first and second transistors;
a pair of current sources, respectively connected in series with the third and fourth transistors, having a common control node coupled to the second conduction node of the first transistor;
wherein, the second conduction node of the second transistor generates the single-end output signal.
2. The converter according to claim 1 , wherein the first and second transistors are first-type transistors, the third and fourth transistors are second-type transistors, and the first-type transistors and the second-type transistors are complementary.
3. The converter according to claim 1 , wherein the pair of current sources comprise a fifth transistor and a sixth transistor respectively connected in series with the third and fourth transistors, and the fifth and sixth transistors have a common control node coupled to the second conduction node of the first transistor.
4. The converter according to claim 1 , wherein operation statuses of the first and second transistors are complementary, and operation statuses of the third and fourth transistors are complementary.
5. The converter according to claim 1 , wherein element sizes of the first and second transistors are substantially the same, element sizes of the third and fourth transistors are substantially the same, and element sizes of the pair of current sources are substantially the same.
6. The converter according to claim 1 , further comprising a high-voltage power line and a low-voltage power line, wherein the two first conduction nodes of the first and second transistors are coupled to the low-voltage current line, and the pair of current sources are coupled to the high-voltage power line.
7. The converter according to claim 1 , wherein the differential input signal is formed by a non-inverted signal and an inverted signal that respectively drive the first and second transistors.
8. The converter according to claim 7 , wherein voltage swings of the non-inverted signal and the inverted signal are smaller than a voltage swing of the single-end output signal.
9. The converter according to claim 8 , wherein the non-inverted signal, the inverted signal and the single-end output signal share a low-logic level.
10. A signal converting method, for converting a differential signal to a single-end signal, the differential signal comprising a non-inverted signal and an inverted signal, the method comprising:
providing an output node that generates the single-end signal;
providing a current source;
controlling the current source according to the non-inverted signal; and
conducting one of a charging path and a discharging path according to the inverted signal, and disconnecting one other of the charging path and the discharging path;
wherein, when the differential signal is in a first logic value, the current source charges the output node via the conducted charging path; when the differential signal is in a second logic value, the output node is discharged via the conducted discharging path.
11. The signal converting method according to claim 10 , wherein the step of controlling the current source according to the non-inverted signal comprises:
controlling a control node of the current source to be coupled to a low-voltage power line according to the non-inverted signal, such that a charging current provided by the current source reaches a maximum.
12. The signal converting method according to claim 10 , further comprising:
controlling the current source to be approximately 0V according to the non-inverted signal when conducting the discharging path according to the inverted signal.
13. The signal converting method according to claim 10 , further comprising:
controlling the control node to be decoupled from a low-voltage power line according to the non-inverted signal when conducting the discharging path according to the inverted signal.