Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
1. A system for generating a clock signal in an integrated circuit (IC), comprising:
a wave clocking circuit configured to generate the clock signal;
a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error; and
a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,
wherein the wave clocking circuit comprises a delay chain with a delay matched to a predetermined delay, and
wherein the control signal is configured to adjust a supply voltage of the IC.
2. The system of claim 1 , wherein the delay chain is configured to produce an output signal having a period that matches substantially the predetermined delay, and wherein the clock signal corresponds to the output signal of the delay chain.
3. The system of claim 2 , wherein the control circuit is further configured to provide the control signal to the wave clocking circuit, and wherein the control signal is configured to adjust the delay chain to adjust the frequency of the clock signal.
4. The system of claim 1 , wherein the delay chain includes a ring oscillator circuit.
5. The system of claim 1 , wherein the delay chain includes a plurality of delay cells coupled in series.
6. The system of claim 1 , wherein the target frequency is configured to be below a maximum logic supported frequency.
7. The system of claim 6 , wherein the control circuit is further configured to limit the control signal to a value at or below a maximum value, the maximum value being configured to result in the frequency of the clock signal at a maximum allowable frequency below the maximum logic supported frequency.
8. The system of claim 1 , further comprising:
a power manager,
wherein the control circuit is further configured to provide the control signal to the power manager, and
wherein the power manager is configured to adjust the supply voltage of the IC responsive to the control signal.
9. The system of claim 8 , wherein the delay chain is responsive to the supply voltage of the IC.
10. The system of claim 8 , wherein the adjusted supply voltage causes the frequency of the clock signal to decrease from a maximum allowable frequency to the target frequency.
11. The system of claim 1 , wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.
12. A method for generating a clock signal for an integrated circuit (IC), comprising:
generating a signal having a period that matches substantially a predetermined delay;
designating the signal as the clock signal;
directly comparing a frequency of the clock signal with a target frequency to generate a frequency error;
generating a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error; and
adjusting a supply voltage of the IC responsive to the control signal.
13. The method of claim 12 , further comprising:
adjusting the period of the signal responsive to the control signal to adjust the frequency of the clock signal.
14. The method of claim 12 , wherein the target frequency is configured to be at or below a maximum logic supported frequency.
15. The method of claim 12 , wherein the period of the signal is responsive to the supply voltage of the IC.
16. The method of claim 12 , wherein the adjusted supply voltage causes the frequency of the clock signal to decrease from a maximum allowable frequency to the target frequency.
17. The method of claim 12 , wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.
18. A system for generating a clock signal for an integrated circuit (IC), comprising:
a wave clocking circuit configured to generate the clock signal;
a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error; and
a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,
wherein the control signal is further configured to adjust a supply voltage of the IC.
19. The system of claim 18 , wherein the frequency of the clock signal to reduce the frequency error is adjusted by the adjustment of the supply voltage of the IC.
20. The system of claim 18 , further comprising:
a delay chain, wherein the delay chain is configured to produce an output signal having a period that matches substantially the predetermined delay, and wherein the clock signal corresponds to the output signal of the delay chain.