Semiconductor memory system
View Patent ↗According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
1. A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories mounted on the substrate, wherein the substrate includes:
a first main surface and a second main surface, the second main surface facing a direction opposite to a direction in which the first main surface is facing;
a first wiring layer provided on the first main surface, the nonvolatile semiconductor memories being mounted on the first wiring layer;
a second wiring layer provided on the second main surface;
a plurality of wiring layers disposed as an inner layer; and
a plurality of insulating layers provided between the first wiring layer, the plurality of wiring layers, and the second wiring layer, wherein
an average value of a wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on a second main surface side with respect to a center line of a layer structure of the substrate, is equal to or greater than an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on a first main surface side with respect to the center line of the layer structure of the substrate,
a difference between the average value of the wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, and the average value of the wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate, is 7.5% or less, and
a wiring density of at least one of the plurality of wiring layers is 80% or greater.
2. The semiconductor device according to claim 1 , wherein
a surface of the first wiring layer is covered by a solder resist.
3. The semiconductor device according to claim 1 , wherein
a surface of the second wiring layer is covered by a solder resist.
4. The semiconductor device according to claim 1 , wherein
the nonvolatile semiconductor memories are NAND-type flash memories.
5. The semiconductor device according to claim 4 , wherein
four NAND-type flash memories are mounted on the first wiring layer side of the substrate.
6. The semiconductor device according to claim 1 , wherein
the substrate has a substantially rectangle shape in a plan view.
7. A system comprising:
a substrate that includes a connector;
a plurality of nonvolatile semiconductor memories mounted on the substrate; and
a computer connected to the connector, wherein
the substrate includes:
a first main surface and a second main surface, the second main surface facing a direction opposite to a direction in which the first main surface is facing;
a first wiring layer provided on the first main surface, the nonvolatile semiconductor memories being mounted on the first wiring layer;
a second wiring layer provided on the second main surface;
a plurality of wiring layers disposed as an inner layer; and
a plurality of insulating layers provided between the first wiring layer, the plurality of wiring layers, and the second wiring layer, wherein
an average value of a wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on a second main surface side with respect to a center line of a layer structure of the substrate, is equal to or greater than an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on a first main surface side with respect to the center line of the layer structure of the substrate,
a difference between the average value of the wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, and the average value of the wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate is 7.5% or less, wherein
a wiring density of at least one of the plurality of wiring layers is 80% or greater.
8. The system according to claim 7 , wherein
the nonvolatile semiconductor memories are NAND-type flash memories.
9. The system according to claim 8 , further comprising:
a volatile memory electrically connected to the nonvolatile semiconductor memories.
10. The system according to claim 7 , further comprising:
a power supply circuit mounted on the substrate, wherein
the computer inputs power supply to the connector,
the connector supplies the input power supply to the power supply circuit, and
the power supply circuit is configured to generate an internal voltage from the input power supply and supply the internal voltage to the nonvolatile semiconductor memories.
11. A semiconductor device comprising:
a substrate that includes a connector, the connector being capable of being connected to a computer;
a drive control circuit mounted on the substrate, the drive control circuit being electrically connected to the connector; and
a plurality of nonvolatile semiconductor memories controlled by the drive control circuit, wherein
the substrate includes:
a first main surface and a second main surface, the second main surface facing a direction opposite to a direction in which the first main surface is facing;
a first wiring layer provided on the first main surface;
a second wiring layer provided on the second main surface;
a plurality of wiring layers disposed as an inner layer; and
a plurality of insulating layers provided between the first wiring layer, the plurality of wiring layers, and the second wiring layer, wherein
an average value of a wiring density of the wiring layers and the second wiring layer, which are disposed on a second main surface side with respect to a center line of a layer structure of the substrate, is equal to or greater than an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on a first main surface side with respect to the center line of the layer structure of the substrate,
a difference between the average value of the wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, and the average value of the wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate, is 7.5% or less,
a wiring density of at least one of the plurality of wiring layers is 80% or greater, and
the drive control circuit is mounted on the first main surface of the substrate.
12. The semiconductor device according to claim 11 , wherein
the connector is provided on a short side of the substrate, and
the nonvolatile semiconductor memories are provided on a side opposite to the connector as viewed from a position of the drive control circuit in a plan view.
13. The semiconductor device according to claim 12 , wherein
the nonvolatile semiconductor memories are NAND-type flash memories.
14. The semiconductor device according to claim 11 , further comprising:
a volatile memory electrically connected to the nonvolatile semiconductor memories.
15. The semiconductor device according to claim 14 , wherein
the connector is provided on a short side of the substrate, and
the volatile semiconductor memory is provided on a same side as the connector as viewed from the nonvolatile semiconductor memories in a plan view.
16. The semiconductor device according to claim 11 , further comprising:
an LED that displays a state of the semiconductor device.
17. The semiconductor device according to claim 1 , wherein
a first average value that is an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate, and a second average value that is an average value of a wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, are both 60% or greater, and
a second value, which is an absolute value of a difference between a wiring density of a wiring layer disposed on the first main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer and a wiring density of a wiring layer disposed on the second main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer, is greater than a first value, which is an absolute value of a difference between the first average value and the second average value.
18. The semiconductor device according to claim 17 , wherein a wiring density of a fourth wiring layer facing a third wiring layer with an insulating layer therebetween is smaller than the first average value, the third wiring layer facing the first wiring layer with an insulating layer therebetween, the third wiring layer and the fourth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.
19. The semiconductor device according to claim 17 , wherein a wiring density of a sixth wiring layer facing a fifth wiring layer with an insulating layer therebetween is smaller than the second average value, the fifth wiring layer facing the second wiring layer with an insulating layer therebetween, the fifth wiring layer and the sixth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.
20. The system according to claim 7 , wherein
a first average value that is an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate, and a second average value that is an average value of a wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, are both 60% or greater, and
a second value, which is an absolute value of a difference between a wiring density of a wiring layer disposed on the first main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer and a wiring density of a wiring layer disposed on the second main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer, is greater than a first value, which is an absolute value of a difference between the first average value and the second average value.
21. The system according to claim 20 , wherein a wiring density of a fourth wiring layer facing a third wiring layer with an insulating layer therebetween is smaller than the first average value, the third wiring layer facing the first wiring layer with an insulating layer therebetween, the third wiring layer and the fourth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.
22. The system according to claim 20 , wherein a wiring density of a sixth wiring layer facing a fifth wiring layer with an insulating layer therebetween is smaller than the second average value, the fifth wiring layer facing the second wiring layer with an insulating layer therebetween, the fifth wiring layer and the sixth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.
23. The semiconductor device according to claim 11 , wherein
a first average value that is an average value of a wiring density of the plurality of wiring layers and the first wiring layer, which are disposed on the first main surface side with respect to the center line of the layer structure of the substrate, and a second average value that is an average value of a wiring density of the plurality of wiring layers and the second wiring layer, which are disposed on the second main surface side with respect to the center line of the layer structure of the substrate, are both 60% or greater, and
a second value, which is an absolute value of a difference between a wiring density of a wiring layer disposed on the first main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer and a wiring density of a wiring layer disposed on the second main surface side with respect to the center line of the layer structure of the substrate and closest to the center line among the plurality of wiring layers disposed as the inner layer, is greater than a first value, which is an absolute value of a difference between the first average value and the second average value.
24. The semiconductor device according to claim 23 , wherein a wiring density of a fourth wiring layer facing a third wiring layer with an insulating layer therebetween is smaller than the first average value, the third wiring layer facing the first wiring layer with an insulating layer therebetween, the third wiring layer and the fourth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.
25. The semiconductor device according to claim 23 , wherein a wiring density of a sixth wiring layer facing a fifth wiring layer with, an insulating layer therebetween is smaller than the second average value, the fifth wiring layer facing the second wiring layer with an insulating layer therebetween, the fifth wiring layer and the sixth wiring layer being wiring layers of the plurality of wiring layers disposed as the inner layer.