Low BER hard-decision LDPC decoder
View Patent ↗A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.
1. A solid state storage device, comprising:
a non-volatile memory controller configured to store data in a non-volatile memory via respective channels of the plurality of channels, wherein the stored data is encoded using a low density parity check code;
the non-volatile memory controller including a hard-decision Low Density Parity Check (LDPC) decoder to decode encoded data received from the non-volatile memory via respective channels of the plurality of channels and provide a decoded data output; and
the hard-decision LDPC decoder dynamically selecting a voting algorithm for LDPC decoding to adjust a strength requirement for bit flipping,
wherein the voting algorithm is selected based on the degree of a variable node and previous syndrome values.
2. The solid state storage device of claim 1 , wherein the voting algorithm comprises an original voting method and at least one weakened voting algorithm.
3. The solid state storage device of claim 2 , wherein the voting algorithm includes at least one strengthened voting algorithm.
4. The solid state storage device of claim 1 , wherein the voting algorithm includes an original voting method and at least one strengthened voting algorithm.
5. The solid state storage device of claim 1 , wherein the voting algorithm is selected to adjust the number of failing check nodes required for a hard-decision bit flip.
6. The solid state storage device of claim 5 , wherein the voting algorithm is adjusted based on the history of syndromes and the degree of a variable node.
7. The solid state storage device of claim 6 , wherein for degree 2 nodes, 2 failing check nodes are required to prompt a flip and a first weakened voting algorithm is utilized.
8. The solid state storage device of claim 7 , wherein for degree 3 nodes, 3 failing check nodes are required to prompt a flip and a second weakened voting algorithm is utilized.
9. The solid state storage device of claim 6 , wherein nodes of at least the fourth degree, utilizing either a weakened or strengthened voting algorithm.
10. The solid state storage device of claim 1 , wherein the hard-decision LDPC decoding includes an iterative sequence of reading addresses and determining syndrome values in which a voting algorithm is selected at each new syndrome value.
11. The solid state storage device of claim 1 , wherein the voting algorithm is selected based on analyzing their effect on error patterns.
12. The solid state storage device of claim 1 including table means for adjusting a voting algorithm.
13. A method to improve the decoding capability of a hard decision Low Density Parity Check (LDPC) decoder, comprising the steps of:
encoding data using a low density parity check code;
storing the encoded data in a non-volatile memory; and
decoding the encoded data stored in the non-volatile memory to provide a decoded data output using the LDPC decoder, wherein the decoding step further comprising:
dynamically selecting a voting technique, based on the degree of a variable node and previous syndrome values, from a set of voting techniques in order to adjust a strength requirement for bit flipping in the hard-decision LDPC decoder.
14. The method of claim 13 , wherein the voting techniques comprise an original voting method and at least one weakened voting method.
15. The method of claim 13 , further comprising adjusting the voting techniques to adjust the number of failing check nodes required for a hard-decision bit flip.
16. The method of claim 15 , wherein the voting techniques are adjusted based on the history of syndromes and the degree of a variable node.
17. The method of claim 16 , wherein for degree 2 nodes, 2 failing check nodes are required to prompt a flip and a first weakened voting method is utilized.
18. The method of claim 16 , wherein for degree 3 nodes, 3 failing check nodes are required to prompt a flip and a second weakened voting technique is utilized.
19. The method of claim 15 , wherein nodes of at least the fourth degree, utilizing either a weakened or strengthened voting technique.
20. The method of claim 15 , wherein the voting techniques include at least one strengthened voting algorithm.
21. The method of claim 13 , wherein the hard-decision LDPC decoding includes an iterative sequence of reading addresses and determining syndrome values in which a voting technique is selected at each new syndrome value.
22. The method of claim 13 , further comprising selecting the voting techniques based on analyzing their effect on error patterns.