IP Library Granted Patent US 9,589,154
Granted Patent B2
US 9,589,154 · App. 14/325,266 · Granted Mar 7, 2017

Programming on-chip non-volatile memory in a secure processor using a sequence number

Inventors: Pramila Srinivasan (Pleasanton, CA); John Princen (Cupertino, CA)
Assignee: Acer Cloud Technology Inc.
G06F21/71G06F21/33G06F21/73H04L9/3213H04L9/3263H04L2209/603
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Quick Facts
Patent No.
US 9,589,154
App. No.
14/325,266
Granted
Mar 7, 2017
Kind
B2
Abstract

An improved secure programming technique involves reducing the size of bits programmed in on-chip secret non-volatile memory, at the same time enabling the typical secure applications supported by secure devices. A technique for secure programming involves de-coupling chip manufacture from the later process of connecting to ticket servers to obtain tickets. A method according to the technique may involve sending a (manufacturing) server signed certificate from the device prior to any communication to receive tickets. A device according to the technique may include chip-internal non-volatile memory to store the certificate along with the private key, in the manufacturing process.

Claims (51)

1. A method comprising:

receiving, using a processor, a request for a device certificate;

initializing, using the processor, a state variable in an on-chip writable memory to an initial value in response to a power up event of a device containing the processor;

generating, using the processor and a function of a secret seed random number and a sequence number, a cryptographic key pair;

identifying a key in the cryptographic key pair, the key comprising one of a public key and a private key in the cryptographic key pair;

incrementing, using the processor, the sequence number;

generating, using the processor, a first random number as a function of the key and the state variable;

creating, using the processor, the device certificate based on the first random number and the request for the device certificate, the device certificate being configured to provide a security signature for accessing protected resources by a secure application.

2. The method of claim 1 , further comprising executing at least a portion of the secure application, the executing using at least a portion of the protected resources.

3. The method of claim 1 , further comprising clearing the state variable from the on-chip writable memory before a power down event of the device.

4. The method of claim 1 , wherein generating the cryptographic key pair comprises using a cryptographically strong encryption algorithm to generate the cryptographic key pair based on the seed random number and the sequence number.

5. The method of claim 1 , wherein generating the first random number comprises instructing, using the processor, a pseudorandom number generator to calculate the first random number.

6. The method of claim 1 , wherein the cryptographic key pair comprises an elliptic cryptographic key pair.

7. The method of claim 1 , wherein the on-chip writable memory comprises an on-chip non-volatile (NV) memory, and the seed random number is stored on the on-chip NV memory.

8. The method of claim 1 , wherein the sequence number is a stored sequence number included in the on-chip writable memory.

9. The method of claim 1 , wherein the processor comprises a secure processor, and the method is executed in one or more of a game console having the secure processor, a media player having the secure processor, an embedded secure device having the secure processor, or a digital device having the secure processor.

10. A system, comprising:

an on-chip non-volatile (NV) memory including a secret seed random number;

an on-chip writable memory including a stored sequence number;

a client-side interface associated with a registered client;

a certificate generation module;

wherein, in operation:

the client-side interface is configured to receive a request for a device certificate and to transmit a validated device certificate;

the certificate generation module is configured to:

initialize a state variable in the on-chip writable memory to an initial value in response to a power up event of a device containing the certificate generation module;

generate a cryptographic key pair using a function of the secret seed random number and the sequence number;

identify a key in the cryptographic key pair, the key comprising one of a public key and a private key in the cryptographic key pair;

increment the sequence number;

generate a first random number as a function of the key and the state variable;

create the validated device certificate based on the first random number and the request for the device certificate, the validated device certificate being configured to provide a security signature for accessing protected resources by a secure application.

11. The system of claim 10 , wherein the certificate generation module is configured to facilitate execution of at least a portion of the secure application on the system, the execution using at least a portion of the protected resources.

12. The system of claim 10 , wherein the certificate generation module is configured to clear the state variable from the on-chip writable memory before a power down event of the device.

13. The system of claim 10 , wherein, when generating the cryptographic key pair, the certificate generation module is configured to use a cryptographically strong encryption algorithm to generate the cryptographic key pair based on the seed random number and the sequence number.

14. The system of claim 10 , wherein, when generating the first random number, the certificate generation module is configured to use a cryptographically strong encryption algorithm to instruct a pseudorandom number generator to calculate the first random number.

15. The system of claim 10 , wherein the cryptographic key pair comprises an elliptic cryptographic key pair.

16. The system of claim 10 , wherein the on-chip writable memory comprises an on-chip non-volatile (NV) memory, and the seed random number is stored on the on-chip NV memory.

17. The system of claim 10 , wherein the processor comprises a secure processor, and the method is executed in one or more of a game console having the secure processor, a media player having the secure processor, an embedded secure device having the secure processor, or a digital device having the secure processor.

18. A system, comprising:

an on-chip non-volatile (NV) memory including a secret seed random number;

an on-chip writable memory including a stored sequence number;

a client-side interface associated with a registered client;

means for generating a certificate;

wherein, in operation:

the client-side interface is configured to receive a request for a device certificate and to transmit a validated device certificate;

the means for generating the certificate is configured to:

initialize a state variable in the on-chip writable memory to an initial value in response to a power up event of a device containing the certificate generation module;

generate a cryptographic key pair using a function of the secret seed random number and the sequence number;

identify a key in the cryptographic key pair, the key comprising one of a public key and a private key in the cryptographic key pair;

increment the sequence number;

generate a first random number as a function of the key and the state variable;

create the validated device certificate based on the first random number and the request for the device certificate, the validated device certificate being configured to provide a security signature for accessing protected resources by a secure application.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2021
From: ACER CLOUD TECHNOLOGY INC.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 055029/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2014
From: PRINCEN, JOHN; SRINIVASAN, PRAMILA
To: BROADON COMMUNICATIONS CORP.
Reel/Frame 033266/0609 →
CHANGE OF NAME Recorded Jul 8, 2014
From: BROADON COMMUNICATIONS CORP.
To: IGWARE INC.
Reel/Frame 033281/0945 →
MERGER Recorded Jul 8, 2014
From: IGWARE INC.
To: ACER CLOUD TECHNOLOGY INC.
Reel/Frame 033281/0948 →
Continuity (4)
Continuation 12576356 · Oct 9, 2009
Division 11601323 · Nov 16, 2006
Provisional Application 60857840 · Nov 9, 2006
Related Publication 20140325240A1 · Oct 30, 2014