Leakage current variability based power management

1. A method to provide a leakage current variability based power management, the method comprising:

receiving computation data from a power controller and one or more processor instruction counters (PICs) of a core of a processor that executes one or more instructions;

generating a table of linear combination samples from the computation data, wherein each of the linear combination samples includes a power usage value for a sub-unit of the core;

generating a micro-architectural leakage map of the core from the linear combination samples within the table, wherein the one or more instructions are grouped based on one or more sub-units of the core associated with each one of the one or more instructions;

in response to detection that a second sub-unit is deactivated based on the micro-architectural leakage map, directing a thread of a subset of the one or more instructions to a first sub-unit;

in response to detection that the first sub-unit is unable to compensate the deactivation of the second sub-unit, reactivating the second sub-unit;

executing a thread migration operation to move the thread from the first sub-unit to the second sub-unit, the thread to be executed by the second sub-unit; and

in response to a completion of an execution of the thread;

moving the thread back to the first sub-unit, and

deactivating the second sub-unit.

2. The method of claim 1 , further comprising:

storing a first set of values for a power and a usage of each one of the one or more instructions executed at one of the linear combination samples, for each one of the linear combination samples; and

storing the first set of values in a set of columns and a row of the table associated with a class for each one of the one or more instructions.

3. The method of claim 2 , further comprising:

computing a second value of a consolidated power and a consolidated usage from the first set of values, for each one of the linear combination samples; and

storing the second value within the row and a consolidated power column of the table, for each one of the linear combination samples.

4. The method of claim 3 , further comprising:

normalizing the second value to a decimal value, wherein a maximum value for the second value is 1.

5. The method of claim 2 , further comprising:

normalizing the first set of values to decimal values, wherein a maximum value for the first set of values is 1.

6. The method of claim 1 , further comprising:

in response to a determination of a first number of equations associated with the linear combination samples within the table to exceed a second number of unknowns associated with the linear combination samples within the table, determining a completeness of the table to initiate a production of the micro-architectural leakage map.

7. The method of claim 6 , further comprising:

generating the micro-architectural leakage map from the equations to illustrate an impact of a fabrication variability of the core that reflects an actual leakage of power of the one or more sub-units of the core.

8. The method of claim 1 , further comprising:

determining an estimate of instruction types of an application executed by the core.

9. The method of claim 8 , further comprising:

determining a performance cost to power down the second sub-unit from the one or more sub-units of the core based on an application of the estimate to the micro-architectural leakage map; and

in response to a determination that the performance cost is below a threshold, transmitting sub-unit gating instructions associated with the second sub-unit to the core.

10. The method of claim 1 , further comprising:

determining a power saving value associated with a power down of the second sub-unit from the one or more sub-units of the core based on the micro-architectural leakage map; and

in response to a determination that the power saving value exceeds a threshold, transmitting sub-unit gating instructions associated with the second sub-unit to the core.

11. The method of claim 1 , further comprising:

determining a performance advantage value associated with a power down of the second sub-unit of the core based on the micro-architecture leakage map; and

in response to a determination that the performance advantage value exceeds a threshold, transmitting sub-unit gating instructions associated with the second sub-unit to the core.

12. A system to provide a leakage current variability based power management, the system comprising:

a memory; and

a processor coupled to the memory, wherein the processor includes one or more cores and is configured to execute a power management application in conjunction with one or more instructions stored in the memory, wherein the power management application is configured to:

receive computation data from a power controller and one or more processor instruction counters (PIC) of one of the one or more cores of the processor;

generate a table of linear combination samples from the computation data, wherein the one or more instructions are grouped based on one or more sub-units of a selected core associated with each one of the one or more instructions, and wherein each of the linear combination samples include a power usage value for a sub-unit of the selected core;

generate a micro-architectural leakage map of the selected core from the linear combination samples within the table;

in response to detection that a second sub-unit being deactivated based on the micro-architectural leakage map, direct a thread of a subset of the one or more instructions to a first sub-unit;

in response to detection that the first sub-unit is unable to compensate the deactivation of the second sub-unit, reactivate the second sub-unit;

execute a thread migration operation to move the thread from the first sub-unit to the second sub-unit, the thread to be executed by the second sub-unit; and

in response to a completion of an execution of the thread;

move the thread back to the first sub-unit, and

deactivate the second sub-unit.

13. The system according to claim 12 , wherein the power management application is further configured to:

store a first set of values for a power and a usage of each one of the one or more instructions executed at one of the linear combination samples, for each one of the linear combination samples;

store the first set of values in a set of columns and a row of the table associated with a class for each one of the one or more instructions;

compute a second value of a consolidated power and a consolidated usage from the first set of values, for each one of the linear combination samples; and

store the second value within the row and a consolidated power column of the table, for each one of the linear combination samples.

14. The system according to claim 13 , wherein the power management application is further configured to:

normalize the first set of values and the second value to a decimal value, wherein a maximum value for each one of the first set of values and the second value is 1.

15. The system according to claim 12 , wherein the power management application is configured to:

in response to a determination of a first number of equations associated with the linear combination samples within the table to exceed a second number of unknowns associated with the linear combination samples within the table, determine a completeness of the table to initiate a production of the micro-architectural leakage map; and

generate the micro-architectural leakage map from the equations to illustrate an impact of a fabrication variability of the core that reflects an actual leakage of power of the second sub-unit from the one or more sub-units of the core.

16. The system according to claim 12 , wherein the power management application is further configured to:

determine an estimate of instruction types of an application executed by the core;

determine a performance cost to power down the second sub-unit from the one or more sub-units of the core based on the estimate applied to the micro-architectural leakage map; and

in response to a determination that the performance cost is below a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.

17. The system according to claim 12 , wherein the power management application is further configured to:

determine a power saving value associated with a power down of the second sub-unit from the one or more sub-units of the core based on the micro-architectural leakage map; and

in response to a determination that the power saving value exceeds a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.

18. The system according to claim 12 , wherein the power management application is further configured to:

determine a performance advantage value associated with a power down of the second sub-unit from the one or more sub-units of the core based on the micro-architecture leakage map; and

in response to a determination that the performance advantage value exceeds a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.

19. A non-transitory computer-readable storage medium with

instructions stored thereon to provide a leakage current variability based power management, the instructions, in response to execution by a processor, cause the processor to:

receive computation data from a power controller and one or more processor instruction counters (PIC) of one of one or more cores of the processor that executes one or more instructions;

generate a table of linear combination samples from the computation data, wherein the one or more instructions are grouped based on a sub-unit of the core associated with each one of the one or more instructions, and wherein each of the linear combination samples include a power usage value for the sub-unit of the core

generate a micro-architectural leakage map of the core from the linear combination samples within the table;

in response to detection that a second sub-unit being deactivated based on the micro-architectural leakage map, direct a thread of a subset of the one or more instructions to a first sub-unit;

in response to detection that the first sub-unit is unable to compensate the deactivation of the second sub-unit, reactivate the second sub-unit;

execute a thread migration operation to move the thread from the first sub-unit to the second sub-unit, the thread to be executed by the second sub-unit; and

in response to a completion of an execution of the thread;

move the thread back to the first sub-unit, and

deactivate the second sub-unit.

20. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions further cause the processor to:

determine an estimate of instruction types of an application executed by the core;

determine a performance cost to power down the second sub-unit of the core based on the estimate applied to the micro-architectural leakage map; and

in response to a determination that the performance cost is below a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.

21. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions further cause the processor to:

determine a power saving value associated with a power down of the second sub-unit of the core based on the micro-architectural leakage map; and

in response to a determination that the power saving value exceeds a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.

22. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions further cause the processor to:

determine a performance advantage value associated with a power down of the second sub-unit of the core based on the micro-architecture leakage map; and

in response to a determination that the performance advantage value exceeds a threshold, transmit sub-unit gating instructions associated with the second sub-unit to the core.