IP Library Patent Application 14327267
Patent Application
App. No. 14/327,267

METHOD AND APPARATUS FOR ACTIVE RANGE MAPPING FOR A NONVOLATILE MEMORY DEVICE

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Quick Facts
Patent No.
US None
App. No.
14/327,267
Abstract

Methods and systems are provided that may include a nonvolatile memory to implement a virtual random access memory space.

Claims (28)

1 . (canceled)

2 . An apparatus comprising:

a non-volatile memory having a plurality of physical pages; and

an interface configured to communicate with a bus according to a dynamic random access memory (DRAM) protocol such that data is transferred in units of DRAM pages, wherein the interface is configured to communicate with the non-volatile memory, wherein the interface is configured to provide an overlay window to map a range of physical pages of the non-volatile memory to an address space corresponding to one or more DRAM pages.

3 . The apparatus of claim 2 , wherein the interface is configured to provide a default overlay window.

4 . The apparatus of claim 2 , wherein the overlay window is configurable during runtime to remap associations between the physical pages and the address spaces of the one or more DRAM pages.

5 . The apparatus of claim 2 , wherein the interface is configured to map the range to the one or more DRAM pages with a range mapping table.

6 . The apparatus of claim 5 , further comprising a content addressable memory (CAM) configured to store one or more translation addresses in the range mapping table.

7 . The apparatus of claim 5 , further comprising a content addressable memory (CAM) configured to store one or more identifiers for one or more translation addresses in the range mapping table.

8 . The apparatus of claim 5 , wherein the non-volatile memory comprises at least one of a Phase-Change Memory (“PCM”), a flash memory, or an Electrically Erasable Programmable Read-Only Memory (“EEPROM”).

9 . A method of mapping memory, the method comprising:

communicating with a bus according to a dynamic random access memory (DRAM) protocol such that data is transferred in units of DRAM pages;

communicating with a non-volatile memory; and

providing an overlay window to map a range of physical pages of the non-volatile memory to an address space corresponding to one or more DRAM pages.

10 . The method of claim 9 , wherein the overlay window comprises a default overlay window.

11 . The method of claim 9 , further comprising configuring the overlay window during runtime to remap associations between the physical pages and the address spaces of the one or more DRAM pages.

12 . The method of claim 9 , further comprising mapping the range to the one or more DRAM pages with a range mapping table.

13 . The method of claim 12 , further comprising storing one or more translation addresses in a content addressable memory (CAM) for the range mapping table.

14 . The method of claim 12 , further comprising storing one or more identifiers for one or more translation addresses in a content addressable memory (CAM) for the range mapping table.

15 . The method of claim 12 , wherein the non-volatile memory comprises at least one of a Phase-Change Memory (“PCM”), a flash memory, or an Electrically Erasable Programmable Read-Only Memory (“EEPROM”).

16 . A controller comprising:

an interface configured to communicate with a bus according to a dynamic random access memory (DRAM) protocol such that data is transferred in units of DRAM pages, wherein the interface is configured to communicate with a non-volatile memory, wherein the interface is configured to provide an overlay window to map a range of physical pages of the non-volatile memory to an address space corresponding to one or more DRAM pages; and

a range mapping table configured to store one or more translation addresses or identifiers for translation addresses.

17 . The controller of claim 16 , wherein the interface is configured to provide a default overlay window.

18 . The controller of claim 16 , wherein the overlay window is configurable during runtime to remap associations between the physical pages and the one or more DRAM page address spaces.

19 . The controller of claim 16 , further comprising a content addressable memory (CAM) configured to store one or more translation addresses in the range mapping table.

20 . The controller of claim 16 , further comprising a content addressable memory (CAM) configured to store one or more identifiers for one or more translation addresses in the range mapping table.

21 . The controller of claim 16 , wherein the non-volatile memory comprises at least one of a Phase-Change Memory (“PCM”), a flash memory, or an Electrically Erasable Programmable Read-Only Memory (“EEPROM”).

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →