Random delay generation for thin-film transistor based circuits
View Patent ↗Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.
1. A monostable oscillator, comprising:
a) a capacitor having a first terminal receiving an input and a second terminal coupled to an input of a delay element;
b) a thin-film field-effect transistor (TFT) having a first source/drain terminal receiving a DC source or supply voltage, a second source/drain terminal coupled to said input of said delay element, and a gate electrically connected to said second source/drain terminal, said TFT being configured to provide a current and/or voltage to said second terminal of the capacitor; and
c) a feedback path comprising the delay element, wherein the delay element comprises (i) an XOR gate or an XNOR gate and (ii) an output terminal, and the output terminal of the delay element is coupled to the first terminal of the capacitor;
wherein said current and/or voltage has a value that falls randomly within a predetermined range.
2. The monostable oscillator of claim 1 , wherein said predetermined range corresponds to an operating current and/or voltage range of said TFT.
3. The monostable oscillator of claim 2 , wherein the randomness of said value is related to one or more variations in a manufacturing process of said TFT.
4. The monostable oscillator of claim 1 , wherein said TFT comprises a printed TFT.
5. The monostable oscillator of claim 1 , wherein said TFT comprises an NMOS TFT.
6. The monostable oscillator of claim 1 , wherein said capacitor has a capacitance that, in conjunction with a resistance of the TFT, provides a desired RC time constant τ.
7. The monostable oscillator of claim 6 , wherein said delay element further comprises one or more inverters, the XOR gate or XNOR gate is configured to (i) receive an output of said one or more inverters at a first terminal thereof and an input signal at a second terminal thereof, and (ii) provide an output coupled to the first terminal of the capacitor, and the RC time constant τ has a duration that varies in accordance with random variations in the capacitance of the capacitor and the resistance of the TFT.
8. The monostable oscillator of claim 6 , wherein the RC time constant τ has a duration that varies in accordance with random variations in the capacitance of the capacitor and the resistance of the TFT.
9. The monostable oscillator of claim 1 , wherein said delay element further comprises one or more inverters, and the XOR gate or XNOR gate is configured to receive an output of said one or more inverters at a first terminal thereof and an input signal at a second terminal thereof, and provide an output coupled to the first terminal of the capacitor.
10. A monostable oscillator, comprising:
a) a capacitor having a first terminal receiving an input and a second terminal coupled to an input of a delay element;
b) a thin-film field-effect transistor (TFT) having a first source/drain terminal receiving a DC source or supply voltage, a second source/drain terminal coupled to said input of said delay element, and a gate electrically connected to said second source/drain terminal, said TFT being configured as a pull-up resistive element configured to provide a current and/or voltage to said second terminal of the capacitor; and
c) a feedback path comprising the delay element, wherein the delay element comprises one or more inverters and an output terminal, and the output terminal of the delay element is coupled to the first terminal of the capacitor;
wherein said current and/or voltage has a value that falls randomly within a predetermined range.
11. The monostable oscillator of claim 10 , wherein said predetermined range corresponds to an operating current and/or voltage range of said TFT.
12. The monostable oscillator of claim 11 , wherein the randomness of said value is related to one or more variations in a manufacturing process of said TFT.
13. The monostable oscillator of claim 10 , wherein said TFT comprises a printed TFT.
14. The monostable oscillator of claim 10 , wherein said TFT comprises an NMOS TFT.
15. The monostable oscillator of claim 10 , wherein said capacitor has a capacitance that, in conjunction with a resistance of the TFT, provides a desired RC time constant τ.
16. The monostable oscillator of claim 15 , wherein said delay element further comprises a logic gate configured to (i) receive an output of said one or more inverters at a first terminal thereof and an input signal at a second terminal thereof, and (ii) provide an output coupled to the first terminal of the capacitor, and the RC time constant τ has a duration that varies in accordance with random variations in the capacitance of the capacitor and the resistance of the TFT.
17. The monostable oscillator of claim 16 , wherein said logic gate comprises an XNOR gate or an XOR gate.
18. The monostable oscillator of claim 10 , wherein said delay element further comprises a logic gate configured to receive an output of said one or more inverters at a first terminal thereof and an input signal at a second terminal thereof, and provide an output coupled to the first terminal of the capacitor.
19. The monostable oscillator of claim 18 , wherein the RC time constant τ has a duration that varies in accordance with random variations in the capacitance of the capacitor and the resistance of the TFT.
20. The monostable oscillator of claim 18 , wherein said logic gate comprises an XNOR gate or an XOR gate.