High electron mobility transistor

1. A high electron mobility transistor, comprising:

a substrate;

an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region;

a matrix electrode structure arranged in the first region comprising a plurality of first electrodes arranged on the epitaxial stack;

a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes;

a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes;

a plurality of first bridges electrically connecting the plurality of second electrodes, wherein one of the bridges is arranged between two of the second electrodes and crossed over one of the first electrodes; and

a plurality of second bridges electrically connecting the plurality of third electrodes.

2. The high electron mobility transistor of claim 1 , wherein the matrix electrode structure further comprises a plurality of first fingers extending from one of the first electrodes.

3. The high electron mobility transistor of claim 2 , further comprising a first pad arranged in the second region, wherein one of the first fingers electrically connects with the one of the first electrode and the first pad.

4. The high electron mobility transistor of claim 2 , wherein the matrix electrode structure further comprises a plurality of second fingers extending from one of the second electrodes.

5. The high electron mobility transistor of claim 4 , wherein the second electrode comprises a first edge and the plurality of second fingers extending from the first edge along a vertical direction.

6. The high electron mobility transistor of claim 4 , wherein one of the first fingers surrounds one of the second fingers.

7. The high electron mobility transistor of claim 4 , wherein a length of one of the first fingers is longer than that of one of the second fingers.

8. The high electron mobility transistor of claim 4 , further comprising a second pad arranged in the second region, wherein one of the second fingers electrically connects with the one of the second electrode and the second pad.

9. The high electron mobility transistor of claim 1 , wherein one of the second bridges is arranged between two of the third electrodes and crosses over one of the first electrodes.

10. The high electron mobility transistor of claim 1 , wherein the matrix electrode structure further comprises a plurality of first fingers extending from one of the first electrodes and/or a plurality of third fingers extending from one of the third electrodes.

11. The high electron mobility transistor of claim 10 , further comprising a third pad arranged in the second region, wherein one of the third fingers electrically connects with one of the third electrode and the third pad.

12. The high electron mobility transistor of claim 11 , wherein the third electrode comprises a second edge and the plurality of third fingers extending from the second edge in a vertical direction.

13. The high electron mobility transistor of claim 10 , wherein one of the first fingers surrounds one of the third fingers.

14. The high electron mobility transistor of claim 1 , wherein more than two first electrodes form a geometric shape surrounding one of the second electrode or the third electrode.

15. The high electron mobility transistor of claim 1 , wherein the plurality of first electrodes and the plurality of second electrodes or the plurality of third electrodes are disposed in different columns or lines.

16. The high electron mobility transistor of claim 1 , wherein the plurality of first electrodes is gate electrode, the plurality of second electrodes is source electrode, and the plurality of third electrodes is drain electrode.

17. The high electron mobility transistor of claim 1 , wherein the substrate comprises a concave region disposed below the first region.

18. The high electron mobility transistor of claim 17 , further comprising a conductive layer arranged in the concave region and an insulating layer arranged between the conductive layer and the substrate.