Testing system for power delivery network

1. A method, comprising:

iteratively receiving, at a control logic block in a field programmable gate array (FPGA), load current amplitude values and a load current frequency values, wherein for each iteration a particular load current amplitude value and a particular load current frequency value is received, and wherein at least two different load current amplitude values are received;

for each iteration:

determining, by the control logic block based on the load current amplitude value received and the load current frequency value received for the iteration:

an activation modulation signal that causes each of a plurality of load cells to which it is applied to be in an active state for a first period of time and in an inactive state during a second period of time, wherein each load cell is in the FPGA and is configured to perform a set of operations at first clock frequency value of a first clock; and

a first of number of load cells that when activated according to the activation modulation signal cause the FPGA to draw a load current at an amplitude that is specified by the load current amplitude value;

selecting, by the control logic block, the first number of load cells in the FPGA; and

providing, by the control logic block, the activation modulation signal to each selected load cells so that activation of each of the selected load cells is modulated according to the activation modulation signal, resulting in the FPGA drawing the load current at the load current amplitude value and at a frequency that is specified by the load current frequency value.

2. The method of claim 1 , wherein the activation modulation signal defines a duty cycle.

3. The method of claim 2 , wherein the load current frequency value is less than the first clock frequency value.

4. The method of claim 3 , wherein determining the activation modulation signal comprises:

dividing the first clock frequency value by the load current frequency value to obtain a modulation count value;

determining a first count value and a second count value that sum to the modulation count value; and

causing the selected load cells to be active for a number of first clock cycles equal to the first count value; and

causing the selected load cells to be inactive for a number of first clock cycles equal to the second count value.

5. The method of claim 4 , wherein the first count and the second count are equal.

6. The method of claim 1 , wherein the load current amplitude value is a peak amplitude value.

7. The method of claim 1 , further comprising monitoring supply voltage and supply current in a power distribution network that provides power to the FPGA.

8. The method of claim 1 , further comprising monitoring the supply voltage and supply current in the power distribution network that provides power to the FPGA for a plurality of load current frequency values at the load current amplitude.

9. A system, comprising:

a testing host system in data communication with a field programmable gate array (FPGA), the testing host system programmed to provide load current amplitude values and load current frequency values to the FPGA, and to monitor supply voltage and supply current in a power distribution network that provides power to the FPGA and associate monitored supply voltage values and supply current values with the load current amplitude values and load current frequency values provided to the FPGA; and

an FPGA including a control logic block and load cells, wherein:

the control logic block is configured to:

iteratively receive load current amplitude values and a load current frequency values, wherein for each iteration a particular load current amplitude value and a particular load current frequency value is received, and wherein at least two different load current amplitude values are received;

for each iteration, determine, based on the load current amplitude value received and the load current frequency value received for the iteration:

an activation modulation signal that causes each of a plurality of load cells to which it is applied to be in an active state for a first period of time and in an inactive state during a second period of time, wherein each load cell is in the FPGA and is configured to perform a set of operations at a first clock frequency value of a first clock;

a first of number of load cells that when in activated according to the activation modulation signal cause the FPGA to draw a load current at an amplitude that is specified by the load current amplitude value;

select the first number of load cells in the FPGA; and

provide the activation modulation signal to each selected load cells so that activation of each of the selected load cells is modulated according to the activation modulation signal, resulting in the FPGA drawing the load current at the load current amplitude value and at a frequency that is specified by the load current frequency value.

10. The system of claim 9 , wherein the activation modulation signal defines a duty cycle.

11. The system of claim 10 , wherein the load current frequency value is less than the first clock frequency value.

12. The system of claim 11 , wherein determining the activation modulation signal comprises:

dividing the first clock frequency value by the load current frequency value to obtain a modulation count value;

determining a first count value and a second count value that sum to the modulation count value; and

causing the selected load cells to be active for a number of first clock cycles equal to the first count value; and

causing the selected load cells to be inactive for a number of first clock cycles equal to the second count value.

13. The system of claim 12 , wherein the first count and the second count are equal.

14. The system of claim 10 , wherein the load current amplitude value is a peak amplitude value.