PACKET HANDLER FOR HIGH SPEED DATA NETWORKS
An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.
1 . An apparatus for routing digital information packets, the apparatus comprising:
a software-programmed processor;
hardware components configured:
to separate incoming packets into packets requiring digital signal processing and packets not requiring digital signal processing;
to separate payload information from header information for the packets requiring digital signal processing; and
to transfer the payload information of the packets requiring digital signal processing to at least one digital signal processor (DSP) via a hardware path which bypasses the software-programmed processor, the DSP being configured to perform digital signal processing on the payload information of the packets requiring digital signal processing to provide processed signal information; and
a transmitter configured to transmit the processed signal information on a network.
2 . The apparatus of claim 1 , wherein the hardware components comprise:
at least one buffer pool configured to buffer the packets requiring digital signal processing; and
at least one buffer pool configured to buffer the packets not requiring digital signal processing.
3 . The apparatus of claim 1 , wherein the hardware components are further configured to separate the incoming packets requiring digital signal processing from the incoming packets not requiring digital signal processing by separating packets associated with real time communication services from packets associated with data services and packets associated with network control.
4 . The apparatus of claim 3 , wherein the hardware components are further configured to separate the packets associated with real time communication services from the packets associated with data services and the packets associated with network control by separating packets associated with voice over packet services from protocol data unit (PDU) packets and media access control (MAC) packets.
5 . The apparatus of claim 1 , wherein the hardware components are further configured to separate payload information from header information for the packets requiring digital signal processing by stripping real time protocol (RTP) information from the packets requiring digital signal processing.
6 . The apparatus of claim 1 , wherein the hardware components are further configured to separate incoming packets requiring digital signal processing from packets not requiring digital signal processing without requiring running of software on the software-programmed processor.
7 . The apparatus of claim 6 , wherein the hardware components configured to separate incoming packets requiring digital signal processing from packets not requiring digital signal processing comprise at least one of:
a specialized logic circuit;
an application specific integrated circuit (ASIC); and
a field programmable gate array (FPGA).
8 . The apparatus of claim 1 , wherein the hardware components are further configured to separate payload information from header information without requiring running of software on the software-programmed processor.
9 . The apparatus of claim 8 , wherein the hardware components configured to separate payload information from header information without requiring running of software on the software-programmed processor comprise at least one of:
a specialized logic circuit;
an application specific integrated circuit (ASIC); and
a field programmable gate array (FPGA).
10 . The apparatus of claim 1 , wherein the hardware components are further configured to transfer the payload information of the packets requiring digital signal processing to the at least one DSP via the hardware path by transferring the payload information on a dedicated hardware bus.
11 . The apparatus of claim 10 , where the dedicated hardware bus is configured for serial transmission.
12 . The apparatus of claim 10 , where the dedicated hardware bus is configured for a transmission protocol supported by the software-programmed processor and by the DSP.
13 . The apparatus of claim 1 , wherein:
the at least one DSP is configured to perform digital to analog conversion of the payload information to provide an analog signal; and
the transmitter is configured to transmit the analog signal on the network.
14 . An apparatus for routing digital information packets, the apparatus comprising:
a software-programmed processor;
a receiver configured to receive incoming payload information from a network; and
a digital signal processor (DSP) configured to perform digital signal processing on the payload information to provide processed payload information; and
hardware components configured:
to add header information to the processed payload information to provide real time service packets; and
to put the data packets into a buffer accessible by the software-programmed processor, the buffer being separate from buffers used for packets associated with data services and packets associated with network control; and
a transmitter configured to transmit the real time service packets on the network, with preference given to the real time service packets over packets associated with data services and over packets associated with network control.
15 . The apparatus of claim 14 , wherein the incoming payload information comprises a voice signal.
16 . The apparatus of claim 14 , wherein the packets associated with voice and data services comprise protocol data unit (PDU) packets and the packets associated with network control comprise media access control (MAC) packets.
17 . The apparatus of claim 14 , wherein the DSP is further configured to add header information to the processed payload information comprises adding real time protocol (RTP) information.
18 . The apparatus of claim 14 , wherein the hardware components are further configured to add header information to the processed payload information without requiring running of software on the software-programmed processor.
19 . The apparatus of claim 14 , wherein the hardware components are further configured to put the data packets into a buffer accessible by the CPU by transferring the data packets into the buffer without requiring running of software on the software-programmed processor.
20 . The apparatus of claim 19 , wherein the hardware components are further configured to transfer the data packets into the buffer without requiring running of software on the software-programmed processor by transferring the packets on a dedicated hardware bus.
21 . The apparatus of claim 14 , wherein the DSP is further configured to perform analog to digital conversion of the payload information to provide a digital signal.