Advanced control circuit for switched-mode DC-DC converter

1. A circuit for controlling a switched-mode DC-DC converter operating in a discontinuous current mode, comprising:

an LC circuit connected between a switching node and an output node, wherein an input voltage applied as a pulse to the switching node charges the LC circuit and develops an output voltage at the output node, and removing the input voltage from the switching node discharges the LC circuit; and

an RC circuit connected in parallel to the LC circuit between the switching node and the output node to compensate for a ripple voltage, the RC circuit having an RC time constant, a first node proximate to the switching node for detecting a positive current sense signal, and a second node proximate to the output node for detecting a negative current sense signal;

wherein a waveform that measures the positive current sense signal at the first node less the negative current sense signal at the second node has a falling edge after the pulse is removed, the RC time constant is selected such that falling edge of the waveform does not become negative, and wherein the RC time constant is increased during the falling edge of the waveform.

2. The circuit of claim 1 , wherein the falling edge of the waveform is controlled to be decreased such that the waveform does not become negative.

3. The circuit of claim 1 , wherein the switching node is driven by a control circuit, further comprising:

a feedback circuit having an output connected to the control circuit;

a resistive network connected to the output node and generating a feedback signal connected to a first input of the feedback circuit; and

a voltage reference connected to a second input of the feedback circuit;

wherein the sum of a voltage at the first node less the voltage at the second node, plus the feedback signal less the voltage reference, multiplied by a scaling factor, is greater than zero after the pulse is removed.

4. The circuit of claim 3 , wherein:

the LC circuit includes an inductor having a first end connected to the switching node and a second end connected in series with an output resistor and an output capacitor;

the RC circuit includes a first branch having a first resistor and a first capacitor connected in series between the switching node and the output node in parallel with the inductor, and a second branch having a sample and hold circuit, a second resistor and a second capacitor connected in series between the first node and the output node, wherein the first node is located at the interconnection of the first resistor and the first capacitor, and wherein the second node is located at the interconnection of the second resistor and the second capacitor; and

wherein the first node and the second node are connected to respective inputs of the feedback circuit.

5. The circuit of claim 4 , further comprising:

a first switch and a third resistor connected in parallel with each other and in series between the first resistor and the sample and hold circuit, wherein the first switch is closed after the pulse is removed to thereby increase the RC time constant of the RC circuit.

6. The circuit of claim 4 , further comprising:

a fourth resistor in series with the first resistor, wherein the first resistor is coupled between the switching node and a third node, and

a first switch and the fourth resistor connected in parallel with each other and in series between the third node and the sample and hold circuit, wherein the first switch is closed after the pulse is removed to thereby increase the RC time constant of the RC circuit.

7. A circuit for controlling a switched-mode DC-DC converter, comprising:

a switching node;

a control circuit connected to the switching node and configured to modulate an input voltage as a pulse to the switching node;

an inductor connected between the switching node and an output node;

an output resistor and an output capacitor connected in series to the inductor;

a pair of feedback resistors connected in series between the output node and ground and having a feedback node at an interconnection between the pair of resistors;

a feedback circuit having a plurality of inputs and an output connected to the control circuit;

a ripple compensation circuit connected in parallel with the inductor and having a first node proximate to the switching node for detecting a positive current sense signal and a second node proximate to the output node for sensing a negative current sense signal, the first node and the second node being coupled to respective inputs of the feedback circuit; and

a multiplier having an output connected to the feedback circuit, and the feedback node and a voltage reference connected as inputs and, the multiplier scaling the inputs by a predefined factor;

wherein after the pulse is removed, a difference signal of the first node less the second node is prevented from becoming negative, wherein the ripple compensation circuit is an RC circuit having an RC time constant, and wherein the RC time constant is increased during a falling edge of the difference signal.

8. The circuit of claim 7 , wherein the difference signal has a falling edge after the pulse is removed, and the falling edge is decreased such that the difference signal does not become negative.

9. The circuit of claim 7 , wherein the RC circuit includes a first branch having a first resistor and a first capacitor connected in series between the switching node and the output node in parallel with the inductor, and a second branch having a sample and hold circuit, a second resistor and a second capacitor connected in series between the first node and the output node, wherein the first node is located at the interconnection of the first resistor and the first capacitor, and wherein the second node is located at the interconnection of the second resistor and the second capacitor.

10. The circuit of claim 9 , further comprising:

a first switch and a third resistor connected in parallel with each other and in series between the first resistor and the sample and hold circuit, wherein the first switch is closed after the pulse is removed to thereby increase the RC time constant of the RC circuit.

11. The circuit of claim 9 , further comprising:

a fourth resistor in series with the first resistor, wherein the first resistor is coupled between the switching node and a third node, and

a first switch and the fourth resistor connected in parallel with each other and in series between the third node and the sample and hold circuit, wherein the first switch is closed after the pulse is removed to thereby increase the RC time constant of the RC circuit.

12. The circuit of claim 7 , wherein the sum of a voltage at the first node less a voltage at the second node, plus the feedback signal less the voltage reference, multiplied by a scaling factor, is greater than zero after the pulse is removed.

13. A method for controlling a switched-mode DC-DC converter operating in a discontinuous current mode, comprising:

coupling an LC circuit between a switching node and an output node, wherein an input voltage applied as a pulse to the switching node charges the LC circuit and develops an output voltage at the output node, and removing the input voltage from the switching node discharges the LC circuit;

coupling an RC circuit in parallel to the LC circuit between the switching node and the output node to compensate for a ripple voltage, the RC circuit having an RC time constant, a first node proximate to the switching node for detecting a positive current sense signal, and a second node proximate to the output node for detecting a negative current sense signal;

detecting a waveform that measures the positive current sense signal at the first node less the negative current sense signal at the second node, wherein the waveform has a falling edge after the pulse is removed, and

selecting the RC time constant such that falling edge of the waveform does not become negative;

further comprising increasing the RC time constant during the falling edge of the waveform.

14. The method of claim 13 , further comprising:

coupling a first branch having a first resistor and a first capacitor in series between the switching node and the output node in parallel with the inductor; and

coupling a second branch having a sample and hold circuit, a second resistor and a second capacitor in series between the first node and the output node, wherein the first node is located at the interconnection of the first resistor and the first capacitor, and wherein the second node is located at the interconnection of the second resistor and the second capacitor.

15. The method of claim 14 , further comprising:

coupling a first switch and a third resistor in parallel with each other and in series between the first resistor and the sample and hold circuit; and

closing the first switch after the pulse is removed thereby increasing the RC time constant of the RC circuit.

16. The circuit of claim 14 , further comprising:

placing a fourth resistor in series with the first resistor;

coupling the first of the pair of resistors between the switching node and a third node;

coupling a first switch the fourth resistor in parallel with each other and in series between the third node and the sample and hold circuit; and

closing the first switch after the pulse is removed thereby increasing the RC time constant of the RC circuit.