IP Library Granted Patent US 8,990,659
Granted Patent B2
US 8,990,659 · App. 14/330,203 · Granted Mar 24, 2015

Efficient re-read operations in analog memory cell arrays

Inventors: Uri Perlmutter (Holon, IL); Naftali Sommer (Rishon Le-Zion, IL); Ofir Shalvi (Ra'anana, IL)
Assignee: Apple Inc.
G06F11/10G06F11/1008
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Quick Facts
Patent No.
US 8,990,659
App. No.
14/330,203
Granted
Mar 24, 2015
Kind
B2
Abstract

A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.

Claims (39)

1. An apparatus, comprising:

a plurality of non-volatile memory cells configured to store data encoded with an Error Correction Code (ECC); and

circuitry coupled to the plurality of non-volatile memory cells, wherein the circuitry is configured to:

read storage values from the plurality of non-volatile memory cells using a first read threshold to generate first values;

decode the ECC dependent upon the first value;

re-read, responsive to a failure of the decoding of the ECC, the storage values from the plurality of non-volatile memory cells, using a second read threshold and a third read threshold to generate second values and third values, respectively, wherein the second read threshold is less than the first read threshold, and wherein the third read threshold is greater than the first read threshold;

identify at least one storage value that potentially caused the failure of the decoding of the ECC dependent upon the second and third values; and

re-read, using a fourth read threshold, the at least one storage value from only a subset of the plurality of non-volatile memory cells including non-volatile memory cells storing the at least one storage value to generate fourth values, wherein a number of cells in the subset of the plurality of non-volatile memory cells is less than a number of cells in the plurality of non-volatile memory cells.

2. The apparatus of claim 1 , wherein the circuitry is further configured to re-decode the ECC dependent upon the fourth values.

3. The apparatus of claim 2 , wherein to re-decode the ECC dependent upon the fourth values, the circuitry is further configured to compute respective soft decoding metrics of the fourth values.

4. The apparatus of claim 1 , wherein to identify the at least one storage value that potentially caused the failure of the decoding of the ECC, the circuitry is further configured to compare the respective values of the first values, the second values, and the third values.

5. The apparatus of claim 1 , wherein the at least one storage value is affected by cross-coupling interference.

6. The apparatus of claim 1 , wherein the circuitry is further configured to compensate for the cross-coupling interference dependent upon the fourth values.

7. A method, comprising:

reading storage values from a plurality of non-volatile memory cells using a first read threshold to generate first values, wherein data stored in the plurality of non-volatile memory cells is encoded with an Error Correction Code (ECC);

decoding the ECC dependent upon the first values;

re-reading, responsive to a failure of the decoding of the ECC, the storage values from the plurality of non-volatile memory cells, using a second read threshold and a third read threshold, to generate second values and third values, respectively, wherein the second read threshold is less than the first read threshold, and wherein the third read threshold is greater than the first read threshold;

identifying at least one storage value that potentially caused the failure of the decoding of the ECC dependent upon the second and third values; and

re-reading, using a fourth read threshold, the at least one storage value from only a subset of the plurality of non-volatile memory cells including non-volatile memory cells storing the at least one storage value to generate fourth values, wherein a number of cells in the subset of the plurality of non-volatile memory cells is less than a number of cells in the plurality of non-volatile memory cells.

8. The method of claim 7 , further comprising re-decoding the ECC dependent upon the fourth values.

9. The method of claim 8 , wherein re-decoding the ECC dependent upon the fourth values comprises computing respective soft decoding metrics of the fourth values.

10. The method of claim 7 , wherein identifying the at least one storage value that potentially caused the failure of the decoding of the ECC comprises comparing the respective values of the first values, the second values, and the third values.

11. The method of claim 7 , wherein the at least one storage value is affected by cross-coupling interference.

12. The method of claim 11 , further comprising compensating for the cross-coupling interference dependent upon the fourth values.

13. The method of claim 7 , wherein each non-volatile memory cell of the plurality of non-volatile memory cells comprises a single-level non-volatile memory cell.

14. The method of claim 7 , wherein each non-volatile memory cell of the plurality of non-volatile memory cells comprises a multi-level non-volatile memory cell.

15. A system, comprising:

a processor; and

a non-volatile memory, wherein the non-volatile memory includes a plurality of non-volatile memory cells, wherein data stored in the plurality of non-volatile memory cells is encoded with an Error Correction Code, and wherein the non-volatile memory is configured to:

read, responsive to a request from the processor, storage values from the plurality of non-volatile memory cells using a first read threshold to generate first values;

decode the ECC dependent upon the first value;

re-read, responsive to a failure of the decoding of the ECC, the storage values from the plurality of non-volatile memory cells, using a second read threshold and a third read threshold to generate second values and third values, respectively, wherein the second read threshold is less than the first read threshold, and wherein the third read threshold is greater than the first read threshold;

identify at least one storage value that potentially caused the failure of the decoding of the ECC dependent upon the second and third values; and

re-read, using a fourth read threshold, the at least one storage value from only a subset of the plurality of non-volatile memory cells including non-volatile memory cells storing the at least one storage value to generate fourth values, wherein a number of cells in the subset of the plurality of non-volatile memory cells is less than a number of cells in the plurality of non-volatile memory cells.

16. The system of claim 15 , wherein the memory is further configured to re-decode the ECC dependent upon the fourth values.

17. The system of claim 16 , wherein to re-decode the ECC dependent upon the fourth values, the memory is further configured to compute respective soft decoding metrics of the fourth values.

18. The system of claim 15 , wherein to identify the at least one storage value that potentially caused the failure of the decoding of the ECC, the memory is further configured to comparing the respective values of the first values, the second values, and the third values.

19. The system of claim 15 , wherein the at least one storage value is affected by cross-coupling interference.

20. The system of claim 19 , wherein the memory is further configured to compensate for the cross-coupling interference dependent upon the fourth values.

Continuity (6)
Continuation 13523421 · Jun 14, 2012
Division 12323544 · Nov 26, 2008
Provisional Application 60991245 · Nov 30, 2007
Provisional Application 61013027 · Dec 12, 2007
Provisional Application 61016566 · Dec 25, 2007
Related Publication 20140325308A1 · Oct 30, 2014