Power semiconductor package
View Patent ↗A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
1. A power semiconductor package comprising:
a semiconductor die that includes a first electrode;
a support plate;
an insulation body disposed over said support plate;
a plurality of laterally spaced conductive pads on said insulation body, a first one of said conductive pads including a first region coupled to said first electrode with a conductive adhesive body and a second region readied for connection to an external conductive pad;
wherein said insulation body electrically insulates said plurality of laterally spaced conductive pads from said support plate.
2. The power semiconductor package of claim 1 , wherein said semiconductor die includes a second electrode lateral to said first electrode, a second one of said conductive pads including a first region coupled to said second electrode with a conductive adhesive body and a second region readied for connection to an external conductive pad.
3. The power semiconductor package of claim 1 , wherein said semiconductor die includes a third electrode.
4. The power semiconductor package of claim 3 , wherein said third electrode is readied for connection to an external conductive pad.
5. The power semiconductor package of claim 3 , further comprising a conductive clip coupled to said third electrode.
6. The power semiconductor package of claim 1 , further comprising a conductive clip coupled to a third conductive pad of said plurality of laterally spaced conductive pads, said third conductive pad including a first region coupled to said conductive clip and a second region readied for connection to an external conductive pad.
7. The power semiconductor package of claim 1 , wherein said plurality of laterally spaced conductive pads extend beyond peripheral edges of said insulation body.
8. The power semiconductor package of claim 1 , wherein said plurality of laterally spaced conductive pads are confined within peripheral edges of said insulation body.
9. The power semiconductor package of claim 1 , wherein said semiconductor die is an IC.
10. The power semiconductor package of claim 1 , wherein said support plate is metallic.