IP Library Granted Patent US 9,129,881
Granted Patent B2
US 9,129,881 · App. 14/331,742 · Granted Sep 8, 2015

Solid-state imaging device with charge holding section between trenched transfer gate sections, manufacturing method of same, and electronic apparatus

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Quick Facts
Patent No.
US 9,129,881
App. No.
14/331,742
Granted
Sep 8, 2015
Kind
B2
Abstract

A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Claims (33)

1. A solid-state imaging device, comprising:

a pixel including a photoelectric conversion element configured to generate a charge in response to incident light, a first transfer gate configured to transfer the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate configured to transfer the charge from the charge holding section to a floating diffusion, wherein

the first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and

the charge holding section includes a semiconductor region positioned between adjacent ones of the plurality of trench gate sections.

2. The solid-state imaging device according to claim 1 , wherein respective ones of the at least two trench gate sections have a dimension in the depth direction which is larger than a dimension in a direction perpendicular to the depth direction.

3. The solid-state imaging device according to claim 1 , wherein a depth of respective ones of the at least two trench gate sections is substantially the same as a depth of the semiconductor region.

4. The solid-state imaging device according to claim 1 , wherein the semiconductor substrate has a first conductivity type and the semiconductor region has a second conductivity type which is opposite the first conductivity type.

5. The solid-state imaging device according to claim 4 , wherein respective portions of the semiconductor substrate are disposed between the semiconductor region and corresponding ones of the at least two trench gate sections.

6. The solid-state imaging device according to claim 5 , wherein the first conductivity type is P-type, and the second conductivity type is N-type.

7. The solid-state imaging device according to claim 5 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.

8. The solid-state imaging device according to claim 1 , wherein the semiconductor region also serves as one of a source or a drain of the second transfer gate.

9. The solid-state imaging device according to claim 1 , wherein the first transfer gate further includes a light-shielding section.

10. The solid-state imaging device according to claim 9 , wherein the light-shielding section includes portion respective portions embedded in corresponding ones of the at least two trench gate sections.

11. The solid-state imaging device according to claim 9 , wherein the light-shielding section includes a portion covering an upper surface and side surfaces of the first transfer gate.

12. The solid-state imaging device according to claim 9 , wherein a material of the light-shielding section is tungsten.

13. The solid-state imaging device according to claim 1 , wherein the at least two trench gate sections is at least three trench gate sections.

14. The solid-state imaging device according to claim 1 , wherein a material of the first transfer gate is polysilicon.

15. The solid-state imaging device according to claim 1 , wherein the pixel further comprises a discharge gate configured to discharge charges accumulated in the photoelectric conversion element.

16. The solid-state imaging device according to claim 1 , wherein the pixel further comprises a reset gate configured to discharge charges held in the floating diffusion.

17. The solid-state imaging device according to claim 1 , wherein the pixel is a back-side illumination type.

18. A method of manufacturing a solid-state imaging device, comprising:

providing a semiconductor substrate;

forming a pixel on the semiconductor substrate, the pixel including a photoelectric conversion element configured to generate a charge in response to incident light, a first transfer gate configured to transfer the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate configured to transfer the charge from the charge holding section to a floating diffusion, wherein

the first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and

the charge holding section includes a semiconductor region positioned between adjacent ones of the plurality of trench gate sections.

19. An electronic apparatus, comprising:

an optical section;

a solid-state imaging device; and

a digital signal processor circuit,

wherein the solid-state imaging device includes:

a pixel including a photoelectric conversion element configured to generate a charge in response to incident light, a first transfer gate configured to transfer the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate configured to transfer the charge from the charge holding section to a floating diffusion, wherein

the first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and

the charge holding section includes a semiconductor region positioned between adjacent ones of the plurality of trench gate sections.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2014
From: KAWAMURA, TAKAHIRO
To: SONY CORPORATION
Reel/Frame 033329/0512 →